Motorola Corporation

Other

Ford Motor Company Limited

Delco Electronics Corporation

Vernon B Goler

Gary L Miller

Stanley E Groves

John J Vaglica

Brian F Wilkie

Mario D Nemirovsky

Rudolf Bettelheim

David Rivera

Robert S Porter

Thomas R Toms

Rollie Morris Fisher

Mark S Ramseyer

Timothy Ernest Litch

Daniel N Debrito

A data processing system includes a central processing unit (CPU) (20), a peripheral bus (32), and an input/output (I/O) coprocessor (38). The CPU (20) and the I/O coprocessor (38) are coupled to the peripheral bus (32). The I/O coprocessor (38) has a plurality of front-end channels (50) for receiving a time-base, and in response, for providing a time-base reference for input signals and generating output signals using the time-base reference. A back-end processor (80) controls operation of the plurality of front-end channels (50) in response to executing instructions. A visibility bus (40), coupled to the back-end processor (80), is for providing visibility of the internal registers of the back-end processor (80) independent of the CPU (20). The visibility is provided for development of the instructions executed by the back-end processor (80).

Data processing system having an input/output coprocessor with a

I/O control modules (25-29) include a timer bus (71, 72) which may be segmented anywhere along its length. As a result, the channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebases by their respective timer bus (71, 72). The channels within one timer bus block (e.g. 86) can be used to perform different function(s) with the potential for no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). In one embodiment, one end of each timer bus (71, 72) is delineated by a master timer bus control channel (61, 63), and the other end of the timer bus is delineated by a slave timer bus control channel (62, 64).

Timer bus structure for an integrated circuit

A method for identifying a principal tooth in a series of teeth extending along at least a portion of a periphery of a rotatable object includes the steps of rotating the rotatable object, setting a counter to a predetermined value, measuring a first tooth in the series of teeth to obtain a first measurement, adding a qualifying value to the measurement to obtain a qualification measurement, measuring a second tooth in the series of teeth to obtain a second measurement, comparing the second measurement to the qualification measurement, and identifying the second tooth as the principal tooth when the second measurement exceeds the qualification measurement.

Method of tooth detection

Timebase channels in different I/O control modules (IOCMs 281-284 in FIG. 16) or on different integrated circuits (300-302 in FIG. 17 ) may provide synchronized, coherent timebase values to different blocks of work and other channels (e.g. 86 in FIG. 2) that are coupled to different timer buses (e.g. 71 in FIG. 2). In one embodiment, referring to FIGS. 1-19, two or more timebase channels, e.g. master timebase channel (285) and slave timebase channel (288), can be synchronized and kept in synchronization using just two signals, namely a clock signal (328) and a synchronization signal (329). The master timebase channel (285) generates or receives a master dock signal (328) which is coupled to one or more slave timebase channels (288) to ensure that the master and slave timebase channels (285, 288) increment or decrement at the same time and rate.

Timebase synchronization in separate integrated circuits or separate

I/O control modules (IOCMs 25-29) include pin/status buses (75-77) which allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Thus, the operation of channels (e.g. 58) can be synchronized with each another. Pin/status buses (75-77) are modular in that they can be extended or alternately segmented to create separate buses carrying different signals. In one embodiment, each end of pin/status bus (75-77) is delineated by a pin control channel (PCCs 51-53). Pin/status buses (75-77) may be used to transfer event information between channels within an IOCM (e.g. IOCM 25), to transfer event information from one IOCM (e.g. 25) to a different IOCM (e.g. 26), and to transfer pin information between integrated circuit pins (31-35) and one or more channels in IOCMs (25-29).

Pin and status bus structure for an integrated circuit

Referring to FIGS. 1 and 2, I/O control modules (IOCMs 25-29) have channels which communicate by way of timer buses (71, 72) and pin/status buses (75-77). Channels (86, 87) are partitioned by each timer bus (71, 72) into separate blocks of channels (86, 87) which are provided with access to different timebase values from timebase channels (80, 81) by their respective timer bus (71, 72), so there is no loss of resolution because each channel in a timer bus block (e.g. 86) can concurrently receive the same timebase value from its corresponding timer bus (71). Pin/status buses (75-77) allow simultaneity of control among the channels (e.g. 58) coupled to the same pin/status bus (e.g. 76). Pin/status buses (75-77) and timer buses (71, 72) can be independently partitioned.

Integrated circuit input/output processor having improved timer

Referring to FIGS. 2, 13, and 14, the tag value transferred by timebase select signals (50) indicates which timebase is presently available on timer bus (71). In one embodiment, each channel (61, 62, 80, 81, and 86) compares the tag value of the timebase select signals (50) with a user programmed tag value stored in a register portion (264). If the stored tag value matches the tag value being driven on the timebase select signals (50), then the match signal (263) is asserted to indicate that the channel is either to provide a timebase value to the timer bus (71) for timebase channels (80, 81), or to receive the timebase value from the timer bus (71) for work and other channels (86). FIG. 15 illustrates examples of how timebase values (namely TB1-TB8) may be selectively provided during the different time slots of a timer bus (e.g. 71).

Flexible configuration of timebases in a timer system

A timer system comprises multiple channels, each of which is capable of performing input and output timer functions referenced to any of a plurality of timer reference signals. In the preferred embodiment, sixteen independent channels are serviced by a processor dedicated to that purpose and each can perform capture and match functions referenced to either of two free-running counters.

Integrated circuit timer with multiple channels and dedicated service

A system comprises a service processor and a plurality of operating units dependent on the service processor. The service processor responds to service requests from the operating units and services the operating units one at a time. A scheduler is responsible for assigning priority to the operating units and determining the order in which the service requests are handled. A register contains a value indicative of the operating unit currently being serviced and is under control of the scheduler. According to one aspect of the present invention the register is also under control of the service processor itself. Another register, under control of the service processor, is coupled to the scheduler to generate service requests thereto independent of the operating units. A memory addressable by the service processor stores data. The service processor is capable of generating addresses for the memory derived from the contents of the register indicative of the operating unit currently being serviced.

Dedicated service processor with inter-channel communication features

A timer subsystem which provides a data processor servicing the timer subsystem with the ability to inhibit the match recognition logic of the timer subsystem while the processor is servicing the subsystem. The disclosed embodiment comprises a sixteen-channel timer subsystem with a dedicated service processor. The service processor, under control of the micro-coded programs executing thereon, is capable of disabling a match recognition latch in the timer channel currently being serviced. This feature provides the ability to prevent unwanted matches which occur while the service processor is updating the match register, for instance. Another feature of the timer subsystem is the inhibition of multiple matches to a single match register value by disabling the match recognition latch upon the occurrence of a match and re-enabling it only when the match register is written by the data processor.

Timer channel with match recognition features

A timer system comprises a plurality of timer channels serviced by a single service processor. Each of the timer channels is capable of both input (capture) and output (match) functions. The microprogrammed service processor is responsible for configuring each of the channels for their intended uses and for responding to service requests generated by the channels in response to the occurrence of timer events. Features of the timer channels include the ability to continuously execute capture functions without generating service requests, the ability to execute a single capture function and service request and protect the captured value from being overwritten until the service request has been responded to and the ability to combine match and capture functions in such a way as to place a time-out window on the capture event.

Timer channel for use in a multiple channel timer system

A timer channel with multiple timer reference signals available to it which is capable of performing any input or output timer function with reference to any of the available reference signals. In addition, input timer functions may be related to the occurrence of output functions. For instance, the state of one timer reference may be captured automatically at a specified time referenced to another timer reference. Another feature of the invention provides for the creation of a time-out window for an input timer function through the use of a concurrent output function.

Growing community of inventors

Austin, TX, United States of America

Vernon B Goler