Lsi Logic Corporation

Lsi Corporation

Nantero, Inc.

Verne C Hornback

Wai Lo

Sey-Shing Sun

Hong Lin

Peter Austin Burke

Derryl D J Allman

Richard J Carter

Claude Louis Bertin

Thomas Rueckes

Wilbur G Catabay

Venkatesh P Gopinath

Derryl D Allman

Wei-Jen Hsia

Richard Carter

James P Kimball

Dodd Defibaugh

Ynhi Thi Le

Mohammad R Mirbedini

Shiqun Gu

Todd A Randazzo

Byung-Sung Kwak

Hemanshu D Bhatt

David W Daniel

John J Seliskar

James R B Elmer

Newell E Chiesl

John Q Walker

Leslie H Allen

Ramanath Ganapathiraman

A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.

Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow

A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.

Self-aligned cell integration scheme

The present invention is directed to structures and methods of fabricating electromechanical memory cells having nanotube crossbar elements. Such memory cells include a substrate having transistor with a contact that electrically contacts with the transistor. A first support layer is formed over the substrate with an opening that defines a lower chamber above the electrical contact. A nanotube crossbar element is arranged to span the lower chamber. A second support layer is formed with an opening that defines a top chamber above the lower chamber, the top chamber including an extension region that extends beyond an edge of the lower chamber to expose a portion of the top surface of the first support layer. A roof layer covers the top of the top chamber and includes an aperture that exposes a portion of the extension region of the top chamber and includes a plug that extends into the aperture in the roof layer to seal the top and bottom chambers. The memory cell further includes an electrode that overlies the crossbar element such that electrical signals can activate the electrode to attract or repel the crossbar element to set a memory state for the transistor.

Isolated metal plug process for use in fabricating carbon nanotube memory cells

The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Incorporating dopants to enhance the dielectric properties of metal silicates

Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Fabrication of trenches with multiple depths on the same substrate

A method of making a thin gate dielectric includes providing a metal silicate on a silicon substrate. Nitrogen is implanted into the metal silicate.

Method of incorporating nitrogen into metal silicate based dielectrics by energized nitrogen ion beams

A method of making a thin gate dielectric includes implanting a barrier substance into a region of a silicon substrate. A capacitance-increasing material is implanted into the silicon substrate. An outside layer of the silicon substrate is oxidized to form a first silicon oxide layer. The silicon substrate is oxidized between the first silicon oxide layer and the region.

Thin gate dielectric for a CMOS transistor and method of fabrication thereof

A receiver for detecting a stream of optical data bits which are transmitted at a predetermined frequency includes a plurality of optically-active devices arranged on an integrated circuit substrate in an array. The plurality of optically-active devices are capable of being positioned to receive the stream of optical data bits which are transmitted as light, and each of the optically active devices is capable of detecting light in an optically active state and generating a detected signal corresponding thereto. A control circuit receives a clock signal at a rate corresponding to the predetermined frequency and generates control signals which cause a different one of the plurality of optically-active devices to be in the optically active state during each successive period and thereby detect the presence of light during each of said successive periods and generate the detected signals corresponding to the data bit stream.

Electronically controlled optically-active device array for high-speed receiving and transmitting of fiber optic signals

A short vertical channel, dual-gate, CMOS FET is fabricated by forming a plurality of channel segments in a starting material that extend longitudinally between source and drain areas. The channel segments are laterally separated from one another by spaces and are preferably formed from pillars of starting material located between the spaces. The pillars are laterally oxidized and the oxidation is removed to reduce the width of the pillars and form the channel segments. A gate structure is formed in the spaces between the channel segments. The width of each pillar is defined by conventional, contemporaneous photolithographic exposure and etching, but the width of each channel segment is substantially less than the width of the etch resistant barrier created photolithographically. The relatively narrow channel widths allow fully-depleted and fully-inverted conductivity characteristics which enhance the conductivity characteristics of the FET despite its reduced size, without silicon on insulator (SOI) constructions or epitaxial substrates.

Subtractive oxidation method of fabricating a short-length and vertically-oriented channel, dual-gate, CMOS FET

A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.

Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same

Techniques for fabricating metal-insulator-metal (MIM) capacitive structures by chemical vapor deposition (CVD) help avoid the formation of a porous metal oxide film at the interface between the lower electrode and the insulating layer. One method of fabricating an integrated circuit includes depositing a first titanium nitride electrode layer on a wafer by CVD and subsequently depositing an insulating layer on the first electrode. The insulating layer can comprise a material selected from the group consisting of titanium oxide (TiO,), titanium oxynitride (TiO,N,), titanium oxycarbonitride (TiO,N,C,) and silicon oxide (SiO,), and is deposited by CVD without exposing the first titanium nitride electrode to atmosphere. A second titanium nitride electrode layer also is deposited on the insulating layer by CVD. The various layers of the capacitive structure, including the insulating layer, can be deposited in situ in a single CVD chamber.

Growing community of inventors

Colorado Springs, CO, United States of America

Verne C Hornback