Sperry Corporation

Vernal M Benrud

George F Nelson

Leslie H Johnson

A first feedback loop to a regulator transistor within the drain circuit of the input field effect transistor (FET) serves to maintain the voltage across the drain-gate junction of the input FET at a constant value consistent with FET operation as a source follower, thereby mitigating junction to junction capacitances within the FET. A second feedback loop created guard circuits on the cases of the input FET and the drain circuit regulator transistor, thereby mitigating junction to external circuitry capacitances. A third feedback loop modifies essentially constant current flow in the source circuit of the input FET in order to compensate for capacitance within that circuit. When utilized in compact form for microprobing of low voltage nanosecond rise time signals, the amplifier demonstrates an effective input capacitance of less than 0.5 picofarads.

Low input capacitance amplifier

A method of and an apparatus for magneto-resistively detecting information in a cross-tie memory system is disclosed. The detector includes a first conductive element, which is the terminating portion of an electrically-conducting wide-narrow edged propagating drive line, and second and third conductive elements that are serially aligned along a magnetic, serrated-edged data track, which three conductive elements form two gaps therebetween. The two gaps are oriented along the data track at respective narrow portions, a first narrow portion which may support a cross-tie but which second narrow portion will not support a cross-tie. A differential sense amplifier is coupled across the two gaps using the second narrow portion as a reference segment to differentially detect the presence vel non of a cross-tie in the first narrow portion.

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Eagan, MN, United States of America

Vernal M Benrud