Asml Netherlands B.v.

Venugopal Vellanki

Stefan Hunsche

Vivek Kumar Jain

Johannes Catharinus Hubertus Mulkens

Jun Ye

Yu Long Cao

Been-Der Chen

Mark Christopher Simmons

A defect prediction method for a device manufacturing process involving processing a pattern onto a substrate, the method comprising: identifying a processing window limiting pattern (PWLP) from the pattern; determining a processing parameter under which the PWLP is processed; and determining or predicting, using the processing parameter, existence, probability of existence, a characteristic, or a combination thereof, of a defect produced from the PWLP with the device manufacturing process.

Process window optimizer

A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.

Process variability aware adaptive inspection and metrology

A method of determining candidate patterns from a set of patterns of a patterning process. The method includes obtaining (i) a set of patterns of a patterning process, (ii) a search pattern having a first feature and a second feature, and (iii) a search condition comprising a relative position between the first feature and the second feature of the search pattern; and determining a set of candidate patterns from the set of patterns that satisfies the search condition associated with the first feature and the second feature of the search pattern.

Method for determining candidate patterns from set of patterns of a patterning process

A method including: obtaining a device design pattern layout having a plurality of design pattern polygons; automatically identifying, by a computer, a unit cell of polygons in the device design pattern layout; identifying a plurality of occurrences of the unit cell within the device design pattern layout to build a hierarchy; and performing, by the computer, an optical proximity correction on the device design pattern layout by repeatedly applying an optical proximity correction designed for the unit cell to the occurrences of the unit cell in the hierarchy.

Method and system for pattern configuration

A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including; determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.

The present invention discloses various system and process embodiments where wafer-metrology and direct measurements of the lithography apparatus characteristics are combined to achieve temporal drift reduction in a lithography apparatus/process using a simulation model. The simulation model may have sub-components. For example, a sub-model may represent a first set of optical conditions, and another sub-model may represent a second set of optical conditions. The first set of optical conditions may be a standard set of illumination conditions, and the second set may be a custom set of illumination conditions. Using the inter-relationship of the sub-models, stability control under custom illumination condition can be achieved faster without wafer metrology.

Growing community of inventors

San Jose, CA, United States of America

Venugopal Vellanki