Qualcomm Incorporated

Venugopal Sanaka

Madan Krishnappa

Mohammed Yousuff Shariff

Satish Raj

Raghavendra Dasegowda

Kelageri Nagaraj

Babu Suriamoorthy

Pavan Kumar Patibanda

Huibo Hou

Vinod Kumar Lakshmipathi

Jagadish Hosmani

Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

Channel less floor-planning in integrated circuits

Aspects of the disclosure are directed to a metal only cell-based power grid (PG) architecture. In accordance with one aspect, the power gird (PG) architecture includes a cell building block structure with a N&#xd7;M grid configuration including N cell building blocks arranged in a first direction and M cell building blocks arranged in a second direction, wherein the first direction and the second direction are orthogonal to one another; and a plurality of power grid (PG) cells, wherein each of the N cell building blocks and each of the M cell building blocks are occupied by a PG cell of the plurality of PG cells.

Cell-based power grid (PG) architecture

A method of reducing the number of hold violations in an integrated circuit comprises: determining a segment, wherein the segment is a connection between a plurality of points; associating at least one path with each segment, wherein the path is a connection of points including a starting point and an endpoint; determining a weight for at least one said segment, wherein the weight is determined by a number of paths associated with the at least one said segment; ranking the segments in a matrix based upon the determined weight associated with at least one of the segments; and inserting a buffer at least one of the segments based upon said ranking.

Segment and bipartite graph based apparatus and method to address hold violations in static timing

Growing community of inventors

San Diego, CA, United States of America

Venugopal Sanaka