Texas Instruments Corporation

Venugopal Puvvada

Jayashree Saxena

Kalpesh Amrutlal Shah

Sugandhini Karunanidhi

Atul Kumar Jain

Rishi Bhooshan

Sampath Kuve

Ananth Somayaji Goda

Prapanna Tiwari

A timing closure analysis associated with SoCs uses voltage drop based standard delay formats (SDFs). Static timing analysis (STA) is implemented using multiple SDFs, one for each mode (ATPG Test, BIST Test, Functional) as contrasted with doing STA with only one worst-case SDF for all modes. The multiple SDFs account for the impact of dynamic voltage drops on delays in addition to static IR drops.

Timing closure for system on a chip using voltage drop based standard delay formats

Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.

Electro-migration (EM) and voltage (IR) drop analysis of integrated circuit (IC) designs

The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.

Reducing time to design integrated circuits including performing electro-migration check

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Venugopal Puvvada