Qualcomm Incorporated

Venugopal Boynapalli

Hyeokjin Lim

Xiangdong Chen

Satyanarayana Sahu

Seung Hyuk Kang

Foua Vang

Mukul Gupta

Ramaprasath Vilangudipitchai

Bilal Zafar

Chulmin Jung

Seid Hadi Rasouli

Venkatasubramanian Narayanan

Kevin Bowles

Venkat Narayanan

Mickael Malabry

Sei Seung Yoon

Hari Rao

Giby Samson

Bharani Chava

Dorav Kumar

Qi Ye

Jose Gabriel Corona

Jonghae Kim

Kern Rim

Jung Pill Kim

Stanley Seungchul Song

Changho Jung

Periannan Chidambaram

Animesh Datta

Esin Terzioglu

Giridhar Nallapati

Arun Babu Pallerla

Deepak Sharma

Peijie Feng

Yandong Gao

Sorin Adrian Dobre

Manish Srivastava

Sung Son

Alex Dongkyu Park

Hanil Lee

Xiao Chen

Radhika Vinayak Guttal

Kashyap Ramachandra Bellur

Renukprasad Hiremath

Rui Chen

Vijay Bantval

Chih-lung Kao

Shitiz Arora

Prabaharan Balu

Hananel Kang

Sagar Suresh Sabade

Jason Cheng

Hari Ananthanarayanan

Seohee Kim

Hyeokjin Bruce Lim

Kevin Robert Bowles

A hybrid flop tray, including: a set of flip-flops cascaded along a scan path, wherein a first subset of one or more of the flip-flops of the set includes fin field effect transistors (FinFETs) each sized with a first number of fins, and a second subset of one or more of the flip-flops of the set includes FinFETs each sized with a second number of fins, wherein the first number of fins is different than the second number of fins; and a control circuit configured to provide control signals to the set of flip-flops.

Hybrid flop tray including different fin size flip-flops

An integrated circuit is disclosed that includes a power supply multiplexer for selecting between a first power supply voltage and a second power supply voltage to provide a selected power supply voltage to a memory. A controller includes a comparator stage having a comparator with switchable inputs so that the comparator stage may control a binary state of a first output signal responsive to whether the first power supply voltage is greater than the second power supply voltage plus a voltage offset of the comparator. Similarly, the comparator stage may control a binary state of a second output signal responsive to whether the first power supply voltage is greater than the second power supply voltage minus the voltage offset. The controller controls the selection by the power supply multiplexer responsive to the binary states of the first and second output signals.

Power level comparator with switching input

At least one integrated power management cell of an IC includes a first cell, which is a 4-height cell, that includes a first continuous n-well, a first power interconnect coupled to a first voltage source associated with a first voltage domain and to the first continuous n-well, a second continuous n-well, a second power interconnect coupled to a second voltage source associated with a second voltage domain and to the second continuous n-well, a first subset of a first voltage level shifter associated with the first voltage domain and coupled to the first power interconnect, and a second subset of the first voltage level shifter associated with the second voltage domain and coupled to the second power interconnect.

Integrated power management cells for gate all around technologies

A MOS IC logic cell includes a plurality of gate interconnects extending on tracks in a first direction. The logic cell includes intra-cell routing interconnects coupled to at least a subset of the gate interconnects. The intra-cell routing interconnects include intra-cell Mx layer interconnects on an Mx layer extending in the first direction. The Mx layer is a lowest metal layer for PG extending in the first direction. The intra-cell Mx layer interconnects extend in the first direction over at least a subset of the tracks excluding every mtrack, where 2&#x2264;m&#x3c;Pand Pis a PG grid pitch. A MOS IC may include at least one MOS IC logic cell, and may further include a first set of PG Mx layer interconnects extending in the first direction over the at least one logic cell. The first set of PG Mx layer interconnects have the pitch P&#x3e;m*P.

Vertical power grid standard cell architecture

Field-effect transistor (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals. A FET circuit is provided that includes a FET that includes a conduction channel, a source, a drain, and a gate. The FET circuit also includes a topside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes a backside metal contact electrically coupled with at least one of the source, drain, and gate of the FET. The FET circuit also includes topside and backside metal lines electrically coupled to the respective topside and backside metal contacts to provide power and signal routing to the FET. A complementary metal oxide semiconductor (CMOS) circuit is also provided that includes a PFET and NFET that each includes a topside and backside contact for power and signal routing.

Field-effect transistors (FET) circuits employing topside and backside contacts for topside and backside routing of FET power and logic signals, and related complementary metal oxide semiconductor (CMOS) circuits

A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

Pseudo-triple-port SRAM bitcell architecture

A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mlayer interconnects on an Mlayer extending in a first direction over the first and second subcells. A first subset of the first set of Mlayer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mlayer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.

Multibit multi-height cell to improve pin accessibility

A system includes: a first power supply; a second power supply; a headswitch disposed between the first power supply and logic circuitry; an enable driver coupling the second power supply to a control terminal of the headswitch; and a voltage generator operable to adjust a control voltage from the second power supply to the control terminal of the headswitch in response to a first voltage level of the first power supply exceeding a reference voltage level.

Systems and methods providing leakage reduction for power gated domains

A MOS device of an IC includes pMOS and nMOS transistors. The MOS device further includes a first Mlayer interconnect extending in a first direction and coupling the pMOS and nMOS transistor drains together, and a second Mlayer interconnect extending in the first direction and coupling the pMOS and nMOS transistor drains together. The first and second Mlayer interconnects are parallel. The MOS device further includes a first Mlayer interconnect extending in a second direction orthogonal to the first direction. The first Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The MOS device further includes a second Mlayer interconnect extending in the second direction. The second Mlayer interconnect is coupled to the first Mlayer interconnect and the second Mlayer interconnect. The second Mlayer interconnect is parallel to the first Mlayer interconnect.

Multiple via structure for high performance standard cells

Metal oxide semiconductor device of an integrated circuit

A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

Standard cell architecture for gate tie-off

In certain aspects of the disclosure, a cell includes a first dummy gate extended along a second lateral direction and on a boundary of the cell, a second dummy gate extended along the second lateral direction and on an opposite boundary of the cell, and a third gate extended along the second lateral direction, wherein the third gate is between the first dummy gate and the second dummy gate. The cell also includes a source between the second dummy gate and the third gate electrically coupled to a power rail. The cell further includes a metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction and above the first dummy gate, the source, and the third gate, wherein the metal interconnect is configured to couple the first dummy gate to the power rail through the source.

In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

High performance cell design in a technology with high density metal routing

According to certain aspects of the present disclosure, a chip includes a first gate, a second gate, a first source, a first source contact disposed on the first source, a metal interconnect above the first source contact and the first gate, a first gate contact electrically coupling the first gate to the metal interconnect, and a first via electrically coupling the first source contact to the metal interconnect. The chip also includes a power rail, and a second via electrically coupling the first source contact to the power rail. The second gate is between the first source and the first gate, and the metal interconnect passes over the second gate.

In certain aspects, a semiconductor die includes a first cell and a second cell. The first cell includes first transistors, and a first interconnect structure interconnecting the first transistors to form a first circuit. The second cell includes second transistors, and a second interconnect structure interconnecting the second transistors to form a second circuit. The first circuit and the second circuit are configured to perform a same function, and a length of the first cell in a first lateral direction is greater than a length of the second cell in the first lateral direction.

Placement methodology to remove filler

Growing community of inventors

San Marcos, CA, United States of America

Venugopal Boynapalli