Scintera Networks, Inc.

Inphi Corporation

Intel Mobile Communications Gmbh

Infineon Technologies Ag

Marvell International Limited

Marvell Asia Pte., Ltd.

Morphics Technology, Inc.

Venugopal Balasubramonian

Debanjan Mukherjee

Abhijit M Phanse

Qian Yu

Abhijit G Shanbhag

Jishnu Bhattacharjee

Edem Ibragimov

Fabian Giroud

Keith Rieken

Paul Chou

Song Chen

Christopher Woodthorpe

Prashant Choudhary

Madabusi Govindarajan

Junqing Phil Sun

Lenin Patra

Gregory R Goslin

Jishnu Bhatacharjee

An integrated Circuit (IC) for use in a network device includes a receiver and a Link Quality Estimation Circuit (LQEC). The receiver is configured to receive a signal over a link and to process the received signal. The LQEC is configured to predict a link quality measure indicative of communication quality over the link in the future, by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.

Link-quality estimation and anomaly detection in high-speed wireline receivers

A device includes a network interface that includes a physical coding sublayer (PCS) unit. The PCS unit receives an Ethernet packet. The PCS unit encode the Ethernet packet into a transmission frame that includes a first set of bit fields corresponding to contents of the Ethernet packet and a second set of bit fields corresponding to control information for the encoding. The PCS unit computes a validity value of the transmission frame, wherein the validity value is based on the first set of bit fields included in the transmission frame. The PCS unit inserts the validity value of the transmission frame into one or more idle bit fields in the second set of bit fields included in the transmission frame. The PCS unit processes the transmission frame for sending to a receiving device over a physical medium.

Controlling false packet acceptance

A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.

Distributed micro instruction set processor architecture for high-efficiency signal processing

A wireless communication base station comprising a plurality of application specific instruction set processors (ASISPs) configured to support one or more processes hosted by the base station, and to track process state information associated with each of the processes; and a memory configured to store the tracked process state information, and when an ASISP of the plurality of ASISPs is reallocated from a first process to a second process, the respective ASISP is configured to retrieve from the memory process state information for the second process.

Distributed micro instructions set processor architecture for high-efficiency signal processing

An apparatus and method for adaptively introducing a compensating signal latency related to a signal latency of a data symbol decision circuit. Adaptive timing control circuitry, including an interpolating mixer implemented as a tapped delay line with correlated tap coefficients, introduces a latency adaptively and substantially matching the latency of the data decision circuit for use within an adaptive equalizer, thereby minimizing the mean-squared error of such decision circuit. This adaptive latency is used in generating the feedback error signal which, in turn, can be used by the feedforward equalizer for dynamically adjusting its adaptive filter tap coefficients.

Adaptive signal latency control for communications systems signals

Systems and methods are disclosed to provide channel monitoring and/or performance monitoring for a communication channel. For example, in accordance with an embodiment of the present invention, an equalizer is disclosed that equalizes for channel distortions and also provides channel and performance monitoring information, such as for example bandwidth estimation, channel identification, signal-to-noise ratio, chromatic dispersion, and/or polarization-mode dispersion.

Channel monitoring and identification and performance monitoring in a flexible high speed signal processor engine

An adaptive signal equalizer with a feedforward filter in which the feedback error signal and corresponding incoming data signal are dynamically aligned in time using signal interpolation, and further, to control the precursor/postcursor filter taps configuration, thereby producing more adaptive filter tap coefficient signals for significantly improved and robust signal equalization.

Adaptive signal equalizer with adaptive error timing and precursor/postcursor configuration control

A continuous time electronic dispersion compensation architecture using feed forward equalization and a non-linear decision feedback equalization forms an output signal by a linear combination of successively delayed versions of the input signal and the sliced output signal weighted by appropriate coefficients. A selected number of taps in the mixer used to generate a corresponding number of coefficients for use in the feed forward equalizer are held to a selected voltage to ensure that the coefficients associated with these two taps do not drift. This causes the other coefficients to converge to a unique minimum square error value. In one embodiment the selected voltage is the maximum system voltage.

Method for robust and stable convergence of blind LMS based adaptation of coefficients for a continuous time FFE-DFE

An adaptive coefficient signal generator for use in an adaptive signal equalizer with fractionally-spaced feedback. The signals representing the feedback tap coefficients are generated in conjunction with a timing interpolation parameter such that the fractionally-spaced feedback circuitry dynamically emulates symbol-spaced feedback circuitry.

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San Jose, CA, United States of America

Venugopal Balasubramonian