Xilinx, Inc.

Venu M Kondapalli

Steven P Young

Manoj Chirania

Martin L Voogel

F Erich Goetting

Philip D Costello

Scott O Frake

Trevor J Bauer

David P Schultz

Ramakrishna K Tanikella

Michael J Hart

Jennifer Wong

Vasisht Mantra Vadi

Raymond C Pang

Jane W Sowards

Prasad Rau

Stephen M Trimberger

Peter H Alfke

Kameswara K Rao

Kamal Chaudhary

Schuyler E Shimanek

Wei Guang Lu

Jason R Bergendahl

Tien Duc Pham

Qi Zhang

P Hugo Lamarche

Erich F Goetting

A programmable logic block provides an improved output delay by bypassing the memory array and multiplexer structure when programmed to function as a random access memory (RAM) and a new value is written to the RAM. A programmable logic block includes memory cells, a multiplexer structure, a memory element, a bypass select multiplexer, and a control circuit. The memory cells implement a RAM driven by a write data input signal and a write enable signal. Each memory cell drives an input terminal of the multiplexer structure. Under the control of the write enable signal, a bypass select multiplexer selects either the write data input signal (in RAM mode) or the output terminal of the multiplexer structure (in another mode), and passes the selected signal to a memory element. Thus, when in RAM mode, write data is simultaneously written to a specified location in the RAM and to the memory element.

Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode

A method and apparatus is provided to implement rapid reconfiguration during either a full, or partial, reconfiguration of a programmable logic device (PLD). Rapid reconfiguration is facilitated by a massively parallel configuration data bus that is created to simultaneously reconfigure the entire height of a reconfiguration memory space. A direct link may be provided to the configuration memory space of the PLD by utilizing interconnect and input/output resources to form the massively parallel configuration data bus. An indirect link may also be provided to the entire configuration memory space by utilizing existing random access memory (RAM) resources within the PLD as configuration bitstream buffers.

Apparatus and method for reconfiguring a programmable logic device

A circuit for generating a delayed output in an input/output port of a device adapted to implement circuits operating on a range of voltages is disclosed. The circuit comprises a first terminal of a delay stage of said input/output port coupled to receive a signal to be output by the circuit; a first pass gate coupled to the first terminal; a capacitor having a first terminal coupled to the output of the first pass gate and a second terminal coupled to ground; a second pass gate coupled to the first terminal of the capacitor; and a second terminal of said delay stage of said input/output port coupled to the second pass gate and outputting a delayed signal based upon the second pass gate. A method of generating a delayed output in an input/output stage of a device adapted to implement circuits operating on a range of voltages is also disclosed.

Circuit for and method of generating a delay in an input/output port of an integrated circuit device

A level translator includes a programmable booster stage that augments the drive level of the level translator under certain conditions. The booster stage is programmably activated. e.g., via a memory cell or control bit, and augments operation of the pull-up stages of a cross-coupled latch within the level translator. When the voltage levels at the high voltage portion of the level translator are reduced below a threshold voltage, the booster stage is activated to maintain proper operation of the level translator despite the reduced voltage levels.

Method and apparatus for a programmable level translator

Interconnect driver circuits that can be used in the interconnect structures of dynamic integrated circuits (ICs) such as dynamic programmable logic devices (PLDs). An exemplary IC includes two or more logic circuits, and two or more self-resetting interconnect driver circuits coupled between the logic circuits. Each self-resetting interconnect driver circuit includes a multiplexer circuit driving a buffer circuit. In a first state, the buffer circuit drives a first value onto the output terminal of the buffer circuit. In a second state, the buffer circuit first drives a second value onto the output terminal of the buffer circuit and then returns to the first state. Several different circuits are described in detail.

Interconnect driver circuits for dynamic logic

A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.

Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure

Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

Data monitoring for single event upset in a programmable logic device

Modular wafers and integrated circuits (ICs), and methods of manufacturing modular ICs. A modular wafer can be optionally divided in various ways to avoid defects while producing a variety of modular ICs. A modular wafer includes an array of element dice separated by a scribe area. The scribe area includes interconnect lines that extend across the scribe area between each adjacent pair of the element dice. Unused interconnect lines can be pulled to a known value using weak pullups or pulldowns. Modular ICs can be manufactured with interconnect lines between each pair of adjacent element dice, in which case a single mask set can be used to manufacture a family of programmable logic devices (PLDs).

Methods and structures of providing modular integrated circuits

A programmable logic block provides N-bit and M-bit (e.g., (N/2)-bit) lookahead functionality for carry chains traversing the logic block, N and M being integers greater than one. An exemplary programmable logic block includes four carry multiplexers that together form a 4-bit lookahead carry chain. The 4-bit lookahead carry chain also provides a 2-bit lookahead output after the second carry multiplexer. Alternatively, the last two bits of the 4-bit lookahead carry chain can be used as a 2-bit lookahead carry chain. In one embodiment, the programmable logic block also includes four function generators associated with the four carry multiplexers. Each function generator drives a select terminal of the associated carry multiplexer. The 4-bit and 2-bit carry chains can be programmably coupled to an interconnect structure of the PLD at the carry out output terminals. In some embodiments, an initialization value can also be provided to the 4-bit and 2-bit carry chains.

Programmable logic block with carry chains providing lookahead functions of different lengths

A programmable lookup table optionally provides two input signals and two output signals to an interconnect structure of a programmable integrated circuit when programmed to function as a random access memory (RAM). An integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure. The LUT can be configured to function as a single-bit wide RAM (e.g., a (2**N)&#xd7;1 RAM) having N input address signals coupled to the interconnect structure and one output signal coupled to the interconnect structure, or as a multi-bit wide RAM (e.g., a (2**(N&#x2212;1))&#xd7;2 RAM) having fewer than N (e.g., N&#x2212;1) input address signals coupled to the interconnect structure and at least two output signals coupled to the interconnect structure. Optionally, the LUT can also be configured as shift register logic, e.g., a 2**(N&#x2212;1)-bit shift register or two 2**(N&#x2212;2)-bit shift registers.

Programmable lookup table with dual input and output terminals in RAM mode

A programmable lookup table for an integrated circuit (IC) optionally provides two input signals and two output signals to an interconnect structure of the programmable IC when programmed to function as shift register logic. According to one embodiment, an integrated circuit includes an interconnect structure and a N-input lookup table (LUT) having input and output terminals coupled to the interconnect structure, where N is a integer. The LUT can be configured to function as a (2**(N&#x2212;1))-bit shift register having a shift in input signal and one output signal coupled to the interconnect structure, or as a two (2**(N&#x2212;2))-bit shift registers having two shift in input signals and two output signals coupled to the interconnect structure. In some embodiments, each bit of the shift register includes two memory cells of the LUT, a first memory cell functioning as a master latch and a second memory cell functioning as a slave latch.

Programmable lookup table with dual input and output terminals in shift register mode

A programmable logic block reduces output delay by bypassing a final slave latch when programmed to function as a shift register. The logic block includes memory cells, a multiplexer structure, and a bypass select multiplexer (BSM). The memory cells are coupled in series to form a shift register controlled by a shift clock, each bit including two paired memory cells implementing master and slave latches. Each memory cell drives an input terminal of the multiplexer structure. The BSM drives a select terminal of the multiplexer structure and selects one signal from each pair of the memory cells. The shift clock drives one data input terminal of the BSM. When in shift register mode, the shift clock simultaneously shifts a value in each master latch to the corresponding slave latch and selects a value from one of the master latches. The output path bypasses the slave latch of the selected bit.

Programmable logic block having improved performance when functioning in shift register mode

A test circuit to test rise delay/fall delay performance on a semiconductor device may comprise a latch to latch data at its input responsive to a clock signal. The latch may source an output signal related to the data latched. A buffer chain may be configured to serially propagate the signal sourced by the latch from the latch output back to the clock input, as the clock signal. A reset/set input of the latch may be configured to receive a reset/set signal from an intermediate node of the buffer chain.

Method of measuring performance of a semiconductor device and circuit for the same

A programmable logic device (PLD) includes dynamic lookup table (LUT) circuits, an interconnect structure implemented in either dynamic or static logic, and optional static logic circuits. Each dynamic LUT circuit has paired true and complement input terminals and provides to the interconnect structure both true and complement output signals pre-charged to a first known value. In some embodiments, the LUT circuits are self-resetting circuits that detect when the paired input signals are valid and evaluate the LUT output values at that time. Once a valid LUT output value has been produced, the LUT resets itself in anticipation of the next valid input condition. In some embodiments, the LUT circuits are implemented using clocked dynamic logic. Routing multiplexers in the interconnect structure can be static or dynamic logic, optionally skewed. Clocked LUTs and routing multiplexers use either of two clock phases under the control of configuration memory cells of the PLD.

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Sunnyvale, CA, United States of America

Venu M Kondapalli