Cypress Semiconductor Corporation

Maxim Integrated Products, Inc.

Other

Longitude Flash Memory Solutions Ltd.

Infineon Technologies LLC

Gigasi Solar, Inc.

Sparkz Inc.

Venkatraman Prabhakar

Igor G Kouznetsov

Krishnaswamy Ramkumar

Long Hinh

Kaveh Shakeri

Bo Jin

David Kuan-Yu Liu

Xiaojun Yu

Ryan Tasuo Hirose

Bogdan I Georgescu

Sungkwon Lee

Vineet Agrawal

Nirmal Ratnakumar

Albert M Bergemont

Ali Keshavarzi

Sarath Chandran Puthenthermadam

Ravindra Manohar Kapre

Santanu Kumar Samanta

Swatilekha Saha

Vijay Raghavan

Jayant Ashokkumar

Frederick B Jenne

Keyhan Sinai

Michael Amundson

Sridevi Rajagopalan Schmidt

Prashant Kumar Saxena

Gary Menezes

Ryan Hirose

Systems and methods related to manufacturing of Lithium-Ion cells and Lithium-Ion cell cathode materials composed of LFP (Lithium Iron Phosphate) or LMFP (Lithium Manganese Iron Phosphate) are disclosed. In one exemplary implementation, there is provided a method of using a Nitrogen-containing plasma to treat the Lithium-Ion cell's LFP or LMFP cathode materials. Moreover, the method may include treating the LFP or LMFP cathode materials before and/or after coating the cathode materials on a metal foil.

Systems and methods involving use of nitrogen-containing plasma to treat lithium iron phosphate cathodes

A method can include, for each row of a nonvolatile memory (NVM) cell array, generating a multiply-accumulate (MAC) result for the row by applying input values on bit lines. Each MAC result comprising a summation of an analog current or voltage that is a function of each input value modified by a corresponding weight value stored by the NVM cells of the row. By operation of at least one multiplexer, one of the rows can be connected to an analog-to-digital converter (ADC) circuit to convert the analog current or voltage of the row into a digital MAC value. A storage element of each NVM cell can be configured to store a weight value that can vary between no less than three different values. Corresponding devices and systems are also disclosed.

Compute-in-memory devices, systems and methods of operation thereof

A method of operating a semiconductor inference device that includes the steps of writing one of multiple analog weight values to memory cells of a non-volatile memory (NVM) array, receiving inputs through a bus system, performing multiply accumulate (MAC) operations based on the inputs and the stored analog weight values, converting results of the MAC operations to outputs, and transmitting the outputs through the bus system.

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof

Systems and methods related to manufacturing of Lithium-Ion cells and Lithium-Ion cell cathode materials are disclosed. In one exemplary implementation, there is provided a method of using a Nitrogen-containing plasma to treat the Lithium-Ion cell cathode materials. Moreover, the method may include treating the cathode materials before and/or after coating the cathode materials on a metal foil.

Methods involving use of nitrogen-containing plasma to treat liquid electrolyte lithium-ion cathode materials

A method of fabricating a multi-level memory cell that includes the steps of forming a shallow trench isolation (STI) in a substrate, performing clean and preclean process such that top surfaces of the STI and substrate are substantially leveled, forming a tunnel dielectric using a radical oxidation process, forming upper and lower silicon oxynitride layers in which an amount of electric charge trapped represents N&#xd7;analog values stored in the multi-level memory cell, N is a natural number greater than 2, forming a blocking dielectric and patterning to form a memory stack, and forming a lightly-doped drain extension (LDD) adjacent to the memory stack by angled implant such that the LDD extends at least partly under the memory stack.

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof

Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.

Embedded SONOS and high voltage select gate with a high-K metal gate and manufacturing methods of the same

A method of performing an operation on a non-volatile memory (NVM) cell of a memory device is disclosed. The pass transistor of the NVM cell is an asymmetric transistor including a source with a halo implant. The source of the pass transistor is coupled to a common source line (CSL) that is shared among NVM cells of a sector of NVM cells. The operation may be performed by applying a first signal to a word line (WLS) coupled to a gate of a memory transistor of the NVM cell and applying a second signal to a bit line (BL) coupled to a drain of the memory transistor of the NVM cell.

Asymmetric pass field-effect transistor for nonvolatile memory

A semiconductor device that has a silicon-oxide-nitride-oxide-silicon (SONOS) based non-volatile memory (NVM) array including charge-trapping memory cells arranged in rows and columns and configured to store one of N&#xd7;analog values. Each charge-trapping memory cells may include a memory transistor including an angled lightly doped drain (LDD) implant extends at least partly under an oxide-nitride-oxide (ONO) layer of the memory transistor. The ONO layer disposed within the memory transistor and over an adjacent isolation structure has the same elevation substantially.

A method to integrate silicon-oxide-nitride-oxide-silicon (SONOS) transistors into a complementary metal-oxide-semiconductor (CMOS) flow including a triple gate oxide structure. The memory device may include a non-volatile memory (NVM) transistor that has a charge-trapping layer and a blocking dielectric, a first field-effect transistor (FET) including a first gate oxide of a first thickness, a second FET including a second gate oxide of a second thickness, a third FET including a third gate oxide of a third thickness, in which the first thickness is greater than the second thickness and the second thickness is greater than the third thickness.

Embedded sonos with triple gate oxide and manufacturing method of the same

Asymmetric pass field-effect transistor for non-volatile memory

A memory device that includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion. The NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell has a memory transistor including an angled lightly doped drain (LDD) implant, and a select transistor including a shared source region with a halo implant. The flash memory portion and the EEPROM portion are disposed within one single semiconductor die. Other embodiments are also disclosed.

Bias scheme for word programming in non-volatile memory and inhibit disturb reduction

A non-volatile memory that includes a shared source line configuration and methods of operating the same to reduce disturbs is provided. In one embodiment, the method includes coupling a first positive high voltage to a first global wordline in a first row of an array of memory cells, and coupling a second negative high voltage (V) to a first bitline in a first column of the array to apply a bias to a non-volatile memory transistor in a selected memory cell to program the selected memory cell. A margin voltage having a magnitude less than Vis coupled to a second global wordline in a second row of the array, and an inhibit voltage coupled to a second bitline in a second column of the array.

Method to reduce program disturbs in non-volatile memory cells

A method for operating a memory device includes the steps of providing a first voltage to a first transistor of a first memory cell and a third transistor of a second memory cell, providing a second voltage to a gate of a second transistor of the first memory cell and a gate of a fourth transistor of the second memory cell, and providing a third voltage to a gate of the first transistor of the first memory cell and a gate of the third transistor of the second memory cell. Other embodiments are also described.

Systems, methods, and apparatus for memory cells with common source lines

A method of making a semiconductor device is provided. The method includes forming a deep well (DWELL) and a well (WELL) in a first region of a substrate, the WELL adjacent a surface of the substrate so that an interface between the WELL and DWELL is exposed on the surface of the substrate. A channel for a DEMOS transistor is formed in the first region over the interface and includes a first channel formed in the WELL and a second channel formed in the DWELL. A gate layer is deposited and patterned to concurrently form in the first region a first gate for the DEMOS transistor and in a second region a second gate for an ESD device. Dopants are implanted in the first and second regions to concurrently form a drain extension of the DEMOS transistor, and an ESD diffusion region of the ESD device.

Growing community of inventors

Pleasanton, CA, United States of America

Venkatraman Prabhakar