Kla Tencor Corporation

Advanced Micro Devices Corporation

Hamamatsu-Photonics K.k.

Kla-Tencor Coporation

Venkatraman Iyer

David Lee Brown

Yung-Ho Alex Chuang

Sunil P Joshi

John Fielden

Guowu Zheng

Masaharu Muramatsu

Hisanori Suzuki

Yasuhito Yoneta

Lance Glasser

Jingjing Zhang

Kurt Lehman

Shinya Otsuka

Henrik Nielsen

Devis Contarato

Marcel Trimpl

Kenneth F Hatch

Mansour Kermat

Rui-Fang Shi

Jehn-Huar Chern

Lih-Huah Yiin

Gil S Lee

Steve Zamek

Jehn-Huar Chem

Alex Chuang

David L Brown

A scanning electron microscope incorporates a multi-pixel solid-state electron detector. The multi-pixel solid-state detector may detect back-scattered and/or secondary electrons. The multi-pixel solid-state detector may incorporate analog-to-digital converters and other circuits. The multi-pixel solid state detector may be capable of approximately determining the energy of incident electrons and/or may contain circuits for processing or analyzing the electron signals. The multi-pixel solid state detector is suitable for high-speed operation such as at a speed of about 100 MHz or higher. The scanning electron microscope may be used for reviewing, inspecting or measuring a sample such as unpatterned semiconductor wafer, a patterned semiconductor wafer, a reticle or a photomask. A method of reviewing or inspecting a sample is also described.

Scanning electron microscope and methods of inspecting and reviewing samples

An imaging sensor assembly includes at least one substrate including a plurality of substrate signal lines. The imaging sensor assembly also includes at least one imaging sensor package disposed on the at least one substrate, the at least one imaging sensor package including at least one imaging sensor disposed on at least one imaging sensor package substrate. The imaging sensor assembly also includes at least one receiver package disposed on the at least one substrate, the receiver package including at least one receiver integrated circuit disposed on at least one receiver package substrate. The imaging sensor assembly also includes at least one electrical interconnect operably coupled to the at least one imaging sensor package and the at least one receiver package. A plurality of data signals are transmitted between the at least one imaging sensor package and the at least one receiver package via the at least one electrical interconnect.

Apparatus for high-speed imaging sensor data transfer

An image sensor for short-wavelength light includes a semiconductor membrane, circuit elements formed on one surface of the semiconductor membrane, and a pure boron layer on the other surface of the semiconductor membrane. An anti-reflection or protective layer is formed on top of the pure boron layer. This image sensor has high efficiency and good stability even under continuous use at high flux for multiple years. The image sensor may be fabricated using CCD (charge coupled device) or CMOS (complementary metal oxide semiconductor) technology. The image sensor may be a two-dimensional area sensor, or a one-dimensional array sensor.

Anti-reflection layer for back-illuminated sensor

A method embodiment includes providing a reticle design data that specify a plurality of printable features that are formed on the wafer using the reticle and a plurality of nonprintable features that are not formed on the wafer using such reticle, wherein the reticle design data is usable to fabricate the reticle. A reduced design database is generated from the reticle design data and this reduced design database includes a description or map of the nonprintable features of the reticle, a description or map of a plurality of cell-to-cell regions of the reticle, and a grayscale reticle image that is rasterized from the reticle design data. The reduced design database, along with the reticle, is transferred to a fabrication facility so that the reduced design database is usable to periodically inspect the reticle in the fabrication facility.

Method and apparatus for database-assisted requalification reticle inspection

A module for high speed image processing includes an image sensor for generating a plurality of analog outputs representing an image and a plurality of HDDs for concurrently processing the plurality of analog outputs. Each HDD is an integrated circuit configured to process in parallel a predetermined set of the analog outputs. Each channel of the HDD can include an AFE for conditioning a signal representing one sensor analog output, an ADC for converting a conditioned signal into a digital signal, and a data formatting block for calibrations and formatting the digital signal for transport to an off-chip device. The HDDs and drive electronics are combined with the image sensor into one package to optimize signal integrity and high dynamic range, and to achieve high data rates through use of synchronized HDD channels. Combining multiple modules results in a highly scalable imaging subsystem optimized for inspection and metrology applications.

Integrated multi-channel analog front end and digitizer for high speed imaging applications

The present invention includes an interposer disposed on a surface of a substrate, a light sensing array sensor disposed on the interposer, the light sensing array sensor being back-thinned and configured for back illumination, the light sensing array sensor including columns of pixels, one or more amplification circuitry elements configured to amplify an output of the light sensing array sensor, the amplification circuits being operatively connected to the interposer, one or more analog-to-digital conversion circuitry elements configured to convert an output of the light sensing array sensor to a digital signal, the ADC circuitry elements being operatively connected to the interposer, one or more driver circuitry elements configured to drive a clock or control signal of the array sensor, the interposer configured to electrically couple at least two of the light sensing array sensor, the amplification circuits, the conversion circuits, the driver circuits, or one or more additional circuits.

Interposer based imaging sensor for high-speed image acquisition and inspection systems

A RAM buffer is provided for managing the address inut lines of a RAM buffer to simulate the operation of two FIFO's therein. In addition, an apparatus is provided for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage transmit and receive FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Also disclosed is an apparatus for transmitting packets from said buffer organized into one or two linked lists. Further, an apparatus is provided for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, an apparatus and a method are provided for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

RAM buffer controller for providing simulated first-in-first-out (FIFO)

A RAM buffer controller for managing the address input lines of a RAM buffer to simulate the operation of two FIFO's therein. Apparatus is included for allowing random access by a node processor in a local area network node using the RAM buffer controller to manage 'transmit and receive' FIFO's to have random access to any address in the address space of the buffer without restriction to FIFO boundaries. Apparatus is also included for transmitting packets from said buffer organized into one or two linked lists. Further, apparatus is included for allowing independent initialization of any of the pointers in the RAM buffer controller which are not currently selected, and for allowing software requests for read or write access by the node processor. Further, apparatus and a method are utilized for recording status and length information at the end of a packet instead of in front thereof and for allowing any incoming packet to be flushed without saving status information or to be flushed while saving its status information.

Improved pointer FIFO controller for converting a standard RAM into a

There is disclosed herein an interface for a peripheral to allow the peripheral to communicate with either synchronous or asynchronous systems. The interface includes a series of flip-flops coupled in a chain to take the combined data strobe and chip select signals from an asynchronous system such as a microprocessor and synchronize the combined signal with the peripheral clock and convert the signal to a pulse. This pulse then emulates the instruction enable pulse received from synchronous microprogrammed systems. If the peripheral is operating in a synchronous sytem, the instruction enable signal from the system is gated through a multiplexer controlled by a mode signal which indicates which mode is active so as to act as the peripheral instruction enable signal. An AND gate gates one bit of the instruction bus with the ANDed chip select and data strobe signals to create a read/write control signal for internal use in controlling the data bus drivers.

Processor to peripheral interface for asynchronous or synchronous

There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a byte clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant byte of the checksum register. A byte wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the bytes of CRC data can be shifted into position through the array one byte per each cycle of the byte clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRS calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be performed on all bytes of a message while excluding some selected number of bits in the first byte is also disclosed.

CRC calculation machine with variable bit boundary

There is disclosed herein a CRC calculation circuit which can calculate CRC checkbits on 8 bits of raw input data per cycle of a group clock. The calculation apparatus uses 8 rows of shifting links with the inputs of each row coupled to the data outputs of the preceding row. Each shifting link shifts its input bit one bit position toward the most significant bit, and selected shifting links perform an exclusive-OR operation between their input bits and the output of an input exclusive-OR gate which exclusive-OR's one input bit with one of the bits in the most significant group of the checksum register. A group wide output bus is used to access the final checkbits from the checksum register by disabling the array of shifting links during the output cycles so that the groups of CRC data can be shifted into position through the array one group per each cycle of the group clock. Preset logic for forcing all logic 1's into the data inputs of the first row of shifting links is provided such the machine can be preset during the first clock cycle of the CRC calculation. Several different architectures are disclosed for allowing separate calculation of CRC bits on a header packet and a data packet where the CRC bits on the data packet may be calculated on the data alone or the data plus the header and the CRC bits for the header. Logic for allowing CRC calculation to be peformed on all groups of a message while excluding some selected number of bits in the first group is also disclosed.

Growing community of inventors

Sunnyvale, CA, United States of America

Venkatraman Iyer