Intel Corporation

Microchip Technology Inc.

Venkatraman Iyer

Darren S Jue

Robert G Blankenship

Debendra Das Sharma

Rahul R Shah

Zuoguo Wu

Mahesh U Wagh

Fulvio Spagna

Sitaraman V Iyer

Arvind A Kumar

Jeff Willey

Ashish Gupta

Jeffrey Charles Swanson

William R Halleck

Dixon Chen

Raj K Ramanujan

Yen-Cheng Liu

Simon P Johnson

Robert J Safranek

Herbert H Hum

Vedaraman Geetha

Bahaa Fahim

Aaron T Spink

Robert H Beers

John Junling Zang

William Harry Nale

Abhishek Das

Yuvraj S Dhillon

Robert A Maddox

Eric M Lee

Sanjay Dabral

Theodore Zale Schoenborn

Gerald S Pasdast

Jeffrey R Wilcox

Naveen Cherukuri

Jeff C Morriss

Selim Bilgin

Mohiuddin M Mazumder

Michael Rentschler

Robin Tim Frodsham

David Stewart Dunning

Michelle C Jen

Shivanand I Akkihal

David M Lee

Narasimha R Lanka

Todd A Hinck

Yanzi Xu

Martin Miller

Lip Khoon Teh

Dennis R Halicki

Kai Xiao

Su Wei Lim

Maarten Kuijk

Allen Jay Baum

Rahul C Shah

Daniel S Froelich

Mark S Birrittella

Thanunathan Rangarajan

Tao Liang

Santanu Chaudhuri

Thorben Link

Jing Fang

Jeffrey C Morriss

Azydee Hamid

John Todd West

Anoop Kumar Upadhyay

Eric Matthew Ching

Shreesh Chhabbi

David D Dunning

Jeffrey Ou

Bernd Sostawa

William T Baggett

Eric Ching

Akshay Pethe

Arvind Kumar

An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.

Extending multichip package link off package

Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface. Also disclosed is a PHY transceiver of a 10SPE PHY, where the transceiver includes a circuitry for controlling a starting polarity of frames.

Starting transmission of a frame with a desired starting polarity, and related systems, methods and devices

On or more examples relate, generally, to an apparatus that includes a reconciliation sublayer of a physical layer, a reduced media independent interface (RMII) of the physical layer, and a logic circuit. Such a logic circuit may operate to receive a changed carrier sense signal provided by the reconciliation sublayer, generate a further changed carrier sense signal at least partially responsive to a prediction that the changed carrier sense signal would cause unintended signaling at the RMII, and provide the further changed carrier sense signal to the RMII.

Changing carrier sense signal generated by a reconciliation sublayer of a physical layer that may cause unintended signaling at a reduced media independent interface (RMII)

A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

High performance interconnect

One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.

Wake source communication according to 10SPE local and remote wake and related systems, methods, and devices

First data is received on a plurality of data lanes of a physical link and a stream signal corresponding to the first data is received on a stream lane identifying a type of the first data. A first instance of an error detection code of a particular type is identified in the first data. Second data is received on at least a portion of the plurality of data lanes and a stream signal corresponding to the second data is received on the stream lane identifying a type of the second data. A second instance of the error detection code of the particular type is identified in the second data. The stream lane is another one of the lanes of the physical link and, in some instance, the type of the second data is different from the type of the first data.

Multichip package link error detection

Described is an architecture for a physical layer device useable with single pair Ethernet in a multidrop bus topology that may operate in a sleep mode and control other devices in network segment to operate in a sleep mode. Some embodiments of the physical layer device may support partial networking in a multidrop network, and mixed networks including the same.

Managing power at a station via a physical layer device and related systems, methods and devices

Described is a digital interface and related systems, method and devices. In some embodiments, an interface may be an interface between a link layer and a physical transmission medium. The interface may be configured for a bit rate and/or reference clock that limits electromagnetic emissions (EME), for example, as compared to a bit rate and/or clock rate specified by interfaces widely used in industry.

Ethernet interface and related systems, methods and devices

Disclosed embodiments relate, generally, to improved data reception handling at a physical layer (PHY). Some embodiments relate to end of line systems that include legacy media access control (MAC) and PHY that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of the end of line systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Disclosed are systems and devices for interfacing media access tuning circuitry that implements collision handling or traffic shaping with a reduced media independent interface (RMII). In some embodiments, an interface circuitry manages emulated signals generated by a media access tuning circuitry in response to detecting that the emulated signals would cause incorrect operation of an RMII. Also disclosed is a physical layer (PHY) device for a multidrop network. In some embodiments the PHY device implements physical layer collision techniques and operable to communicate with a media access control (MAC) device via an RMII, where the MAC is configured for carrier-sense multiple access (CSMA), CSMA with collision detection (CSMA/CD), or CSMA with collision avoidance (CSMA/CA). Also disclosed are processes for managing signaling at a PHY that implements physical layer collision avoidance (PLCA) or traffic shaping, as the case may be.

Interface for improved media access, and related systems, methods, and devices

Disclosed are systems, methods, and devices for communicating a source of a 10SPE wake. Such a communication may be performed over a low-pin count hardware interface of a 10SPE physical layer (PHY) module having a split arrangement. A controller side of a 10SPE PHY may perform a local or remote 10SPE wake forward in response to a communicated source of a wake. Also disclosed is a digital interface for operatively coupling a PHY controller to PHY transceiver over a low-pin count connection, where the digital interface includes circuitry for checking the integrity of circuitry of the digital interface.

Low connection count interface wake source communication according to 10SPE local and remote wake and related systems, methods, and devices

Disclosed embodiments relate, generally, to improved data reception handling at a physical layer. Some embodiments relate to end of line systems that include legacy media access control (MAC) devices and PHY devices that implement improved data reception handling disclosed herein. The improved data reception handling improves the operation of legacy systems, and the MAC more specifically, and in some cases to comply with media access tuning protocols implemented at the physical layer.

Physical layer to link layer interface and related systems, methods and devices

Various embodiments relate to a wired local area network (WLAN) including a shared transmission medium (e.g., a 10SPE network). A method may include detecting an event in a WLAN including physical level collision avoidance (PLCA). The method may also include disabling a beacon of a first node operating as a master of the WLAN in response to the event. Further, the method may include enabling a second node to operate as the master of the WLAN.

Changing a master node in a wired local area network and related systems, methods, and devices

Growing community of inventors

Austin, TX, United States of America

Venkatraman Iyer