Micron Technology Incorporated

Globalfoundries Inc.

Marvell Asia Pte., Ltd.

International Business Machines Corporation

Nan Ya Technology Corporation

Globalfoundries U.S. Inc.

Venkatraghavan Bringivijayaraghavan

Jason M Brown

George Maria Braceras

Krishnan Santhana Rengarajan

Igor Arsovski

Sreejith Chidambaran

Arjun Sankar

Sreenivasula Reddy Dhani Reddy

Binu Jose

Scott James Derner

Saravanan Sethuraman

Kenneth Lee Wright

Stephen R Porter

Abhay S Dixit

Ethan Williford

Aravindan J Busi

Scot M Graham

Deepak I Hanagandi

Dhani Reddy Sreenivasula Reddy

Saurabh Chadha

Abhijit Saurabh

Navin Agarwal

Vinay Bhatsoori

Tyler J Gomm

Kang-Yong Kim

Brian W Huber

Darren Lane Anand

Hyun Yoo Lee

Vijayakrishna J Vankayala

Ramesh Raghavan

Rahul Nayak

Puneet Suri

Sheikh Sabiq Chishti

Vinay Bhat Soori

Anoop Delampady

Prasad Vernekar

Jason McBride Brown

Eswararao Potladhurthi

Sreenivasa Chaitanya Kumar Vavilla

Sathisha Nanjundegowda

Apparatuses and techniques for implementing an asymmetric read-write sequence for interconnected dies are described. The asymmetric read-write sequence refers to an asymmetric die-access sequence for read versus write operations. The 'asymmetric' term refers to a difference in an order in which data is written to or read from interface and linked dies of the interconnected die architecture. The orders for the read and write operations can be chosen such that a delay associated with transferring data between the interconnected dies occurs as data passes between the interface die and a memory controller. With asymmetric read-write burst sequences, overall timing of the read and write operations of a memory device may be impacted less, if at all, by a timing delay associated with the interconnected die architecture.

Asymmetric read-write sequence for interconnected dies

Disclosed is a processing unit for computing a convolution of an activations matrix (e.g., a N&#xd7;N activations matrix) and a weights kernel (e.g., a M&#xd7;M weights kernel). The processing unit specifically employs an array of processing elements and a hardware-implemented spiral algorithm to compute the convolution. Due to this spiral algorithm, the need for a discrete data setup logic block is avoided, activation values from the activations matrix can be pre-loaded into processing elements only one time so that the need to repeatedly access the activations matrix is avoided, and the computation can be completed in a relatively low number of clock cycles, which is independent of the number of activation values in the activation matrix and which is equal to the number of weight values in a weights kernel. Also disclosed is an associated processing method.

Processing unit and method for computing a convolution using a hardware-implemented spiral algorithm

A memory architecture and a processing unit that incorporates the memory architecture and a systolic array. The memory architecture includes: memory array(s) with multi-port (MP) memory cells; first wordlines connected to the cells in each row; and, depending upon the embodiment, second wordlines connected to diagonals of cells or diagonals of sets of cells. Data from a data input matrix is written to the memory cells during first port write operations using the first wordlines and read out from the memory cells during second port read operations using the second wordlines. Due to the diagonal orientation of the second wordlines and due to additional features (e.g., additional rows of memory cells that store static zero data values or read data mask generators that generate read data masks), data read from the memory architecture and input directly into a systolic array is in the proper order, as specified by a data setup matrix.

Multi-port memory architecture for a systolic array

A memory device includes a memory array of memory cells, wordlines and bitlines connected to the memory cells, a first read multiplexor and a second read multiplexor connected to the bitlines, a first sense amplifier connected to the first read multiplexor, a second sense amplifier connected to the second read multiplexor, a first data path connected to the first sense amplifier, and a second data path connected to the second sense amplifier. Each of the memory cells is connected to only one pair of the bitlines and only one of the wordlines. The first read multiplexor is adapted to connect the first sense amplifier to the bitlines during a first portion of a clock cycle and the second read multiplexor is adapted to connect the second sense amplifier to the bitlines during a second portion of a clock cycle that is different from the first portion of the clock cycle.

Multi-sense amplifier based access to a single port of a memory cell

Disclosed is a row address comparator with voltage level shifting and latching functionality and including: an evaluation section for comparing two row addresses in a first voltage domain and outputting an initial match signal in a second voltage domain; and a latch section for outputting a latched final match signal based on the initial match signal. The comparator employs a first clock signal (CLK), a second clock signal (CLK) that is different from CLKand a third clock signal (CLK) that is inverted with respect to CLK. CLKsandcontrol pre-charge and evaluation operations within the evaluation section with CLKbeing set to minimize hold time. CLKsandcontrol the latch operation within the latch section. Feedback loops in both sections enhance performance. Also disclosed are a control circuit that incorporates the comparator and a method for implementing row redundancy in a memory.

Row address comparator for a row redundancy control circuit in a memory

Multiple sense amplifier and data path-based pseudo dual port SRAM

Disclosed is a skewed sense amplifier with data and reference sides. The data side has two or more series connected n-type field effect transistors (NFETs) between a data input/output node and a switch to a ground. The reference side has one or more series connected NFETs (but fewer than on the data side) between a reference input/output node and the switch. The data input/output node controls the NFET(s) on the reference side and vice versa. Due to a faster current flow rate through the reference side NFET(s) as compared to the data side NFETs, this amplifier is particularly suited for detecting when, at the initiation of a sensing process, the reference input/output node has a high voltage state and the data input/output node has either a high voltage state or a discharging voltage state. Also disclosed is a memory circuit that incorporates such amplifiers for single-ended read operations.

Skewed sense amplifier for single-ended sensing

A circuit includes a core having a memory array. The memory array includes memory cells and bitlines, and is arranged in columns. The core includes a metallization layer having connections to the memory array, which is devoid of memory cells. Digit lines are connected to the bitlines of a column of the memory array. A write driver is connected to the digit lines. A write assist circuit is connected to the write driver. The write assist circuit maintains a voltage on the digit lines prior to write operations and provides a boost voltage to the digit lines during write operations. A wire bridge located in the metallization layer of the core connects the write assist circuit to the write driver.

Write assist

Disclosed is a chip with a memory array and at least one positive voltage boost circuit, which provides positive voltage boost pulses to the sources of pull-up transistors in the memory cells of the array during write operations to store data values in those memory cells and, more specifically, provides positive voltage boost pulses substantially concurrently with wordline deactivation during the write operations to ensure that the data is stored. Application of such pulses to different columns can be performed using different positive voltage boost circuits to minimize power consumption. Also disclosed are a memory array operating method that employs a positive voltage boost circuit and a chip manufacturing method, wherein post-manufacture testing is performed to identify chips having memory arrays that would benefit from positive voltage boost pulses and positive voltage boost circuits are attached to those identified chips and operably connected to the memory arrays.

Column-dependent positive voltage boost for memory cell supply voltage

The present disclosure relates to a structure which includes at least one bit line restore device which is configured to precharge a bit line to a specified voltage during an intracycle time between a read operation and a write operation and is configured to be turned off during the read operation and the write operation.

Intracycle bitline restore in high performance memory

Embodiments of the present disclosure provide a circuit structure including: first PMOS and second PMOS each including a gate, source, and drain; wherein sources of first and second PMOS are coupled to first voltage source, gate of first PMOS is cross coupled to drain of second PMOS, gate of second PMOS is cross coupled to drain of first PMOS, drain of the first PMOS is coupled to first bit-line node, and wherein drain of second PMOS is coupled to second bit-line node; write bit-switch having first NMOS coupled to first bit-line node and second NMOS coupled to second bit-line node, wherein first and second NMOS of write bit-switch are respectively coupled to a pair of data nodes each receiving one of a pair of data inputs; and write driver, having a pair of transistor stacks each coupled to between one of the pair of data nodes and ground.

Integrated level translator

The present disclosure relates to a circuit, including a first transistor with a drain connected to a capacitor, a gate connected to an input of an inverter and a source connected to ground, a second transistor with a drain connected to the capacitor and a gate connected to the input of the inverter, a third transistor with a source connected to an output of the inverter, a drain connected to a source of the second transistor, and a gate connected to the input of the inverter, and a fourth transistor with a source connected to the source of the third transistor, a drain connected to ground, and a gate connected to the capacitor.

Bending circuit for static random access memory (SRAM) self-timer

A structure includes a write bit switch device which includes a plurality of bit switch devices positioned at different positions of a memory cell array, and which is configured to enable write operations at a specified number of cells per bit line using a strapped bit line on a selected column of the memory cell array.

Bit line strapping scheme for high density SRAM

A circuit includes a memory array having memory cells and bitlines. A write driver is connected to the bitlines through column select transistors. A write assist circuit is connected to the write driver. The write assist circuit includes a common boost node, negative boost transistors, and a keeper transistor. The negative boost transistors are connected from the digit lines to the common boost node. The negative boost transistors selectively pull the bitlines of a selected cell of the memory array to ground during a write operation to the selected cell of the memory array. The write assist circuit may include a first negative boost transistor connected from a first digit line to the common boost node, a second negative boost transistor connected from a second digit line to the common boost node, and a keeper transistor connected from the common boost node to ground.

Hybrid stack write driver

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Cheyyar, India

Venkatraghavan Bringivijayaraghavan