Texas Instruments Corporation

Hewlett Packard Enterprise Development LP

Venkatesh Natarajan

Alexander Tessarolo

Prasanth Viswanathan Pillai

Richard Mark Poley

Alan Davis

Badrish Adiga H R

Karthikeyan Rajamanickam

Ajit Deepak Gupte

Peter N Ehlig

Vinayak Joshi

Saya Goud Langadi

Amitabh Menon

David R Matt

Saumya Dikshit

Ankit Kumar Sinha

Subash Chandar Govindarajan

Rajendra Sadananad Marulkar

Ameet Suresh Bagwe

Vijay Sindagi

Khiruthigai Balasubramanian

Glenn Harland Hopkins

Badrish Adiga Hr

M R Karthikeyan

Various embodiments of the present disclosure relate to conditional branch instructions to support software pipelining techniques. In an example embodiment, a system including instruction fetch circuitry, decoder circuitry, and conditional branch circuitry is provided. The instruction fetch circuitry is configured to fetch a conditional branch instruction from memory and provide the instruction to the decoder circuitry. The instruction includes an iteration count and multiple branch destinations. The branch destinations include two or more branch destinations corresponding to conditions against which the conditional branch circuitry evaluates the iteration count. The decoder circuitry is configured to cause the conditional branch circuitry to select a branch destination, of the two or more branch destinations, based on a comparison of the iteration count to each of the conditions and cause the instruction fetch circuitry to fetch an indication of an instruction from a memory location stored at the selected branch destination.

Conditional branch instructions

A processor with instruction storage configured to store processor instructions, data storage configured to store processor data representing an array, the array including plural data elements, a controller, and an instruction pipeline. The instruction pipeline includes: a load stage circuit configured to load an array element from the data storage, a compare stage circuit configured to compare the array element to a reference value, a store stage circuit configured to store a set of results that includes a result of the comparison of the array element to the reference value, and a loop hit detect stage circuit configured to determine whether any of the set of results is associated with a hit on the reference value.

Reducing overhead in processor array searching

One embodiment provides a system which facilitates scaling of routing in an EVPN. During operation, the system determines, in an Ethernet Virtual Private Network (EVPN), a plurality of virtual tunnel endpoints (VTEPs) coupled to a plurality of subnets, wherein a respective subnet includes one or more hosts, wherein a first VTEP is configured with a first number of host routes for a first subnet coupled to a second VTEP, and wherein each of the first number of host routes corresponds to a host residing in the first subnet. Responsive to detecting that a total number of routes configured on the first VTEP exceeds a first predetermined threshold, the system aggregates the first number of host routes by replacing the first number of host routes with a first prefix route which indicates the first subnet.

Method and system to scale routing in Ethernet Virtual Private Network Symmetric Integrated Routing and Bridging deployments

In described examples, an apparatus is arranged to generate a linear term, a quadratic term, and a constant term of a transcendental function with, respectively, a first circuit, a second circuit, and a third circuit in response to least significant bits of an input operand and in response to, respectively, a first, a second, and a third table value that is retrieved in response to, respectively, a first, a second, and a third index generated in response to most significant bits of the input operand. The third circuit is further arranged to generate a mantissa of an output operand in response to a sum of the linear term, the quadratic term, and the constant term.

Transcendental function evaluation

A processor includes a central processing unit (CPU) and diagnostic monitoring circuitry. The diagnostic monitoring circuitry is coupled to the CPU. The diagnostic monitoring circuitry includes a monitoring and cyclic redundancy check (CRC) computation unit. The monitoring and CRC computation unit is configured to detect execution of a diagnostic program by the CPU, and to compute a plurality of CRC values. Each of CRC values corresponds to processor values retrieved from a given register of the CPU or from a bus coupling the CPU to a memory and peripheral subsystem while the CPU executes the diagnostic program.

Processor with non-intrusive self-testing

One aspect provides a method and system for managing address resolution requests in a network. During operation, a gateway of the network advertises a route for sending address resolution requests and determines whether a cached entry corresponding to an address resolution request received via the route exists in a neighbor table. In response to determining that the cached entry exists, the gateway responds to the address resolution request based on the cached entry; in response to determining that the cached entry does not exist, the gateway replicates the address resolution request to edge devices in the network, thereby facilitating discovery of a target host corresponding to the address resolution request.

System and method for optimizing ARP broadcast

A processor is provided and includes a core that is configured to perform a decode operation on a multi-instruction packet comprising multiple instructions. The decode operation includes receiving the multi-instruction packet that includes first and second instructions. The first instruction includes a primary portion at a fixed first location and a secondary portion. The second instruction includes a primary portion at a fixed second location between the primary portion of the first instruction and the secondary portion of the first instruction. An operational code portion of the primary portion of each of the first and second instructions is accessed and decoded. An instruction packet including the primary and secondary portions of the first instruction is created, and a second instruction packet including the primary portion of the second instruction is created. The first and second instructions packets are dispatched to respective first and second functional units.

Instruction packing scheme for VLIW CPU architecture

One embodiment provides a system and method for managing, at a network node, a data structure indicating neighbor node address information. During operation, the system can determine, based on a media access control (MAC) address or an Internet protocol (IP) address associated with an entry in the data structure, a type of the entry, and set a timeout value for the entry based on the determined type. In response to detecting that an entry corresponding to the MAC address expires in a MAC table maintained by the network node, the system can identify an interface on the network node to which a neighbor associated with the MAC address was previously coupled and transmit a unicast neighbor-probe packet on the identified interface to determine a connection status of the neighbor.

System and method for dynamic tuning of neighbor aging

A processor (and method) includes a core that performs a floating point division through execution of various instructions. The instructions include a sign, exponent, and mantissa (SEM) separation instruction which causes the core to extract the sign, exponent and mantissa values from numerator and denominator floating point numbers. The instructions also include an unsigned mantissa division instruction which cause the core to iteratively perform a conditional subtraction operation to compute a value indicative of a mantissa of the quotient. The instructions further include a merge instruction that causes the core to generate a quotient floating point number using the extracted sign and exponent from the SEM separation instruction and the value indicative of the mantissa of the quotient.

Architecture and instruction set to support interruptible floating point division

A processor includes a core and a plurality of registers including a first register, a second register, and a third register. The core is configured to perform a division operation that includes execution of a sign extraction instruction in which a sign of at least one of a numerator value and a denominator value is stored, a conditional subtraction instruction which divides the numerator value by the denominator value to generate a quotient value and a remainder value, and a sign assignment instruction which adjusts the sign of at least one of the quotient and remainder values. The conditional subtraction instruction is configured to cause the core to perform multiple iterations of a conditional subtraction in one execution of the conditional subtraction instruction and in one clock cycle. Others methods and apparatus are described as well.

Architecture and instruction set to support integer division

Examples disclosed herein relate to security actions that can be taken at a network appliance based on a received copy of a neighbor discovery packet. The neighbor discovery packet copy is received on a control plane of a network that originated at a port on a data plane of the network. The neighbor discovery packet copy includes identification information including an internet protocol address, a media access control address, and information about the port. The identification information is compared to a binding state table to determine that the internet protocol address and the media access control address match the binding state table, but the port does not match a previous port on the binding state table for the internet protocol address. A security action is performed.

Growing community of inventors

Bengaluru, India

Venkatesh Natarajan