Lattice Semiconductor Corporation

Venkatesan Rajappan

Mohan Tandyala

Hua Xue

Sunil Sharma

Nilanjan Chatterjee

Mohana Tandyala

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a method includes identifying a multiplexer in the design, identifying one or more irrelevant inputs for the multiplexer by, at least in part, decomposing the select logic into one or more select line binary decision diagrams corresponding to the one or more select lines, and generating a reduced multiplexer by eliminating the one or more irrelevant inputs from the multiplexer. The reduced multiplexer may be used to generate configuration data to configure physical components of the PLD, and the configuration data may be used to program the PLD to conform to the timing constraints of the design and/or PLD.

Multiplexer reduction for programmable logic devices

Techniques are provided to assign a set/reset signal of a user design to global set/reset (GSR) resources of a programmable logic device (PLD). By assigning a set/reset signal of the user design to the GSR resources during synthesis and prior to mapping, configurable resources consumed by the design may be reduced. In one example, a method includes receiving a user design for a programmable logic device (PLD) that comprises a plurality of configurable resources and global set/reset (GSR) resources. The method also includes identifying a plurality of set/reset signals of the user design. The method also includes determining, for each set/reset signal, a measurement of configurable resource savings associated with an assignment of the set/reset signal to the GSR resources. The method also includes assigning a selected one of the set/reset signals to the GSR resources based on the associated measurement. Additional methods and related systems are also provided.

Early global set/reset signal determination for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD and synthesizing the design into a plurality of PLD components. The synthesizing includes detecting a mixed-mode memory operation in the design. The mixed-mode memory operation specifies memory access having different read and write data widths using a plurality of embedded memory blocks each having a fixed data width. The synthesizing further includes determining a reduced number of embedded memory blocks to implement the mixed-mode memory operation, and modifying the mixed-mode memory operation to remap the memory access to the reduced number of embedded memory blocks.

Mixed-width memory techniques for programmable logic devices

Various techniques are provided to generate designs for programmable logic devices (PLDs). In one example, a computer-implemented method includes selectively grouping a first plurality of logic components for a first design into a plurality of partitions. The method also includes selectively merging at least a subset of the partitions of the first design. The method also includes converting each partition into a corresponding first physical implementation for a PLD. The method also includes comparing the first plurality of logic components to a second plurality of logic components for a second design to identify changed and unchanged partitions. The method also includes converting each changed partition into a corresponding second physical implementation for the PLD. The method also includes combining the first physical implementations for the unchanged partitions, with the second physical implementations for the changed partitions.

Partition based design implementation for programmable logic devices

Various techniques are provided to efficiently implement user designs in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a programmable logic device (PLD). The computer-implemented method also includes synthesizing the design into a plurality of PLD components comprising a first logic block cascaded into a second logic block. In the computer-implemented method, the second logic block implements a multiplexer adapted to selectively pass a first multi-bit input signal received from the first logic block or a second multi-bit input signal. The computer-implemented method also includes further synthesizing the design to absorb the multiplexer into the first logic block.

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Fremont, CA, United States of America

Venkatesan Rajappan