Sunpower Corporation

Total Marketing Services

Maxeon Solar Pte. Ltd.

Zeptor Corporation

Venkatasubramani Balu

David D Smith

Kieran Mark Tracy

Scott Harrington

Ann P Waldhauer

Staffan Westerberg

Asnat Masad

Timothy Weidman

Seung Bum Rim

Taiqing Qiu

Peter John Cousins

Tatsunori Suzuki

Amada Lorena Montesdeoca Santana

Westerberg Staffan

Charles D Consorte

Michelle M Rincon

Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell includes a substrate. A semiconductor structure is disposed above the substrate. The semiconductor structure includes a P-type semiconductor layer disposed directly on a first semiconductor layer. A third semiconductor layer is disposed directly on the P-type semiconductor layer. An outermost edge of the third semiconductor layer is laterally recessed from an outermost edge of the first semiconductor layer by a width. An outermost edge of the P-type semiconductor layer is sloped from the outermost edge of the third semiconductor layer to the outermost edge of the third semiconductor layer. A conductive contact structure is electrically connected to the semiconductor structure.

Tri-layer semiconductor stacks for patterning features on solar cells

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region.

Solar cell emitter region fabrication with differentiated P-type and N-type region architectures

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell can include a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed over an exposed outer portion of the first polycrystalline silicon emitter region and is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. Metallization methods, include etching techniques for forming a first and second conductive contact structure are also described.

Metallization of solar cells with differentiated p-type and n-type region architectures

Methods of fabricating solar cell emitter regions with differentiated P-type and N-type region architectures, and the resulting solar cells, are described herein. In an example, a solar cell includes an N-type semiconductor substrate having a light-receiving surface and a back surface. A plurality of N-type polycrystalline silicon regions is disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate. A plurality of P-type polycrystalline silicon regions is disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate.

Solar cells having differentiated P-type and N-type architectures

Metallization of solar cells with differentiated P-type and N-type region architectures

A method of processing a silicon substrate can include etching the silicon substrate with a first etchant having a first concentration and etching with a second etchant having a second concentration. In an embodiment, the second concentration of the second etchant can be greater than the first concentration of the first etchant. In one embodiment, the first etchant can be a different type of etchant than the second etchant. In an embodiment, the first and second etchant can be the same type of etchant. In some embodiments the silicon substrate can be cleaned with a first cleaning solution to remove contaminants from the silicon substrate prior to etching with the first etchant. In an embodiment, the silicon substrate can be cleaned with a second cleaning solution after etching the silicon substrate with a second etchant.

Sequential etching treatment for solar cell fabrication

A method of fabricating a solar cell can include forming a first dopant region over a silicon substrate and an oxide region over the first dopant region. In an embodiment, the oxide region can protect the first dopant region from a first etching process. In an embodiment, a second dopant region can be formed over the silicon substrate, where a mask can be formed to protect a first portion of the second dopant region from the first etching process. In an embodiment, the first etching process can be performed to expose portions of the silicon substrate and/or a silicon region. A second etching process can be performed to form a trench region to separate a first and second doped region of the solar cell. A third etching process can be performed to remove contaminants from the solar cell and remove any remaining portions of the oxide region.

Etching processes for solar cell fabrication

A current conductor for an electrochemical power device that includes an array of carbon nanotubes (CNT) anchored in a carbon nanotube metal composite layer and a structure that may incorporate nanoscale particles or thin film onto the current conductor is described. Additionally, a process for creating the structure using electrochemical plating of the metal layer onto the CNT array followed by separation of the structure from the substrate is provided. Another process includes creating the structure using co-electrodeposition of the CNT and metal from an electroplating bath using surfactants, physical energy, and a magnetic and/or electric field to orient the CNT and enhance the CNT density in the composite.

Carbon nanotube composite structures and methods of manufacturing the same

Growing community of inventors

Santa Clara, CA, United States of America

Venkatasubramani Balu