Globalfoundries U.S. Inc.

Globalfoundries Inc.

Globalfoundries Singapore Pte. Ltd.

Venkata Narayana Rao Vanukuru

Zhong-Xiang He

Varuna AnanthaPadmanabha Baipadi

Muhammed Shafi Kunnathodi

Anthony K Stamper

Randy Lee Wolf

Kenneth John Giewont

Kevin K Dezfulian

Ranjan Rajoo

Prateek Kumar Sharma

Shyam Parthasarathy

A structure includes a first layer having inductor windings. An inner area of the first layer is at least partially enclosed by the inductor windings and an outer area of the first layer is separated from the inner area by the inductor windings. This structure further includes a second layer having structural fill elements. The first layer and the second layer are parallel, and the second layer is relatively below the first layer in a direction perpendicular to the first layer. The density of the structural fill elements aligned below the inner area is less than the density of the structural fill elements aligned below the outer area.

Inductor with increasing outer fill density

A structure including a first chip and a second chip stacked over the first chip is provided. The first chip includes a first dielectric over a substrate. The second chip includes a second dielectric over the first dielectric. An inductor is arranged at least in part in the first dielectric of the first chip. An electromagnetic shield structure is arranged around the inductor. The electromagnetic shield structure includes a lower shield portion extending at least partially through the first dielectric of the first chip and an upper shield portion extending at least partially through the second dielectric of the second chip. The electromagnetic shield structure is formed in part in the BEOL metallization structure in each of the first chip and the second chip in a heterogenous integration process.

Shielded inductor structures and methods of forming the same

The present disclosure relates to semiconductor structures and, more particularly, to series inductors and methods of manufacture. A structure includes a plurality of wiring levels each of which include a wiring structure connected in series to one another. A second wiring level being located above a first wiring level of the plurality of wiring levels. A wiring structure on the second wiring level being at least partially outside boundaries of the wiring structure of the first wiring level.

Series inductors

Structures including an inductor and methods of forming such structures. The structure comprises a semiconductor substrate including a first plurality of sealed cavities and a back-end-of-line stack on the semiconductor substrate. Each sealed cavity includes an air gap, and the back-end-of-line stack includes an inductor having a winding that overlaps with the scaled cavities.

Inductors with airgap electrical isolation

The embodiments herein relate to packages of semiconductor devices having a shielding element and methods of forming the same. An assembly is provided. The assembly includes a semiconductor chip having a passive component and a package within which the semiconductor chip is positioned in. The package includes a shielding element and a package conductive component, and the package conductive component is electrically coupled with the passive component of the semiconductor chip.

Shielding elements for packages of semiconductor devices

The present disclosure relates to semiconductor structures and, more particularly, to uniplanar (e.g., single layer) passive circuitry and methods of manufacture. The structure includes: passive circuitry comprising plural components each of which are formed on a same wiring level; and interconnects on the same wiring level connecting the plural components of the passive circuitry.

Uniplanar (single layer) passive circuitry

The present disclosure relates generally to semiconductor structures, and more particularly, to structures and methods for implementing high performance vertically stacked inductors and transformers. The structure includes: a first conductor composed of a redistribution line; a second conductor composed of a back end of line wiring layer, coupled to the redistribution line; and a ferro magnetic material between the first conductor and the second conductor.

Vertically stacked inductors and transformers

This disclosure relates generally to semiconductors, and more particularly, to structures and methods for implementing high performance multi-frequency inductors with airgaps or other low-k dielectric material. The structure includes: a plurality of concentric conductive bands; a low-k dielectric area selectively placed between inner windings of the plurality of concentric conductive bands; and insulator material with a higher-k dielectric material than the low-k dielectric area selectively placed between remaining windings of the plurality of concentric conductive bands.

Multi-frequency inductors with low-k dielectric area

A multi-port inductor structure for use in semiconductor applications such as high-performance RF filters and amplifiers is provided. Embodiments of the present invention may provide 3 metallization layers and two via layers. The metallization layers and via layers may be substantially stacked on top of each other to conserve space. Each metallization layer comprises a ring pattern. In embodiments, the top two ring patterns include a plurality of concentric bands, forming a spiral pattern. The third (bottom) ring may include a broken ring pattern. In embodiments, the second (middle) ring may include one or more spans to facilitate connection to the inner bands of the second ring. The spans connect inner bands to an outer perimeter region of the second ring. Multiple tap points along the bands and spans allow multiple inductance values to be obtained from the structure.

Growing community of inventors

Bengaluru, India

Venkata Narayana Rao Vanukuru