Nxp Usa, Inc.

Nxp B.v.

Venkata Naga Koushik Malladi

Joseph Staudinger

Michael Lee Fraser

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. A first network of one or more balancing capacitors includes a first capacitor coupled across multiple transistors of the first plurality of transistors. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. A second network of one or more balancing capacitors includes a second capacitor coupled across multiple transistors of the second plurality of transistors.

Switch circuits with parallel transistor stacks and capacitor networks for balancing off-state RF voltages, and methods of their operation

Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

Quadrature hybrid with variable capacitor tuning network

Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack. In addition, multiple FET stacks are implemented in parallel in at least some switch branches to improve settling time for the branch.

Radio frequency switches with voltage equalization

Embodiments described herein include radio frequency (RF) switches that may provide increased power handling capability. In general, the embodiments described herein can provide this increased power handling by equalizing the voltages across transistors when the RF switch is open. Specifically, the embodiments described herein can be implemented to equalize the source-drain voltages across each field effect transistor (FET) in a FET stack that occurs when the RF switch is open and not conducting current. This equalization can be provided by using one or more compensation circuits to couple one or more gates and transistor bodies in the FET stack in a way that at least partially compensates for the effects of parasitic leakage currents in the FET stack.

A switch circuit includes a transistor stack coupled between first and second ports. The transistor stack includes a group of multiple, adjacent, series-coupled transistors, and at least one additional transistor coupled in series with the group between the first and second ports to provide a first variably-conductive path between the first and second ports. The switch circuit also includes a balancing capacitor with a first terminal coupled to an input of the group of multiple, adjacent, series-coupled transistors, and a second terminal coupled to an output of the group of multiple, adjacent, series-coupled transistors.

Switch circuits and transistor stacks with capacitor networks for balancing off-state RF voltages and methods of their operation

A switch circuit includes first and second transistor stacks coupled in parallel between first and second ports. The first transistor stack includes a first plurality of transistors coupled in series between the first and second ports to provide a first variably-conductive path between the first and second ports. Each transistor of the first plurality of transistors has a gate terminal coupled to a first control terminal. The second transistor stack includes a second plurality of transistors coupled in series between the first and second ports to provide a second variably-conductive path between the first and second ports. Each transistor of the second plurality of transistors has a gate terminal coupled to a second control terminal. When implemented in a transceiver, first and second drivers are configured to simultaneously configure the first and second variably-conductive paths in a low-impedance state.

Switch circuits with parallel transistor stacks and methods of their operation

Various embodiments relate to an amplifier circuit including: a first transistor having a first and second current conducting terminals and a control terminal; a second transistor having a first and second current conducting terminals and a control terminal, in which the second current-conducting terminal of the first transistor is connected to the first current-conducting terminal of the second transistor; a first inductor with a first terminal coupled to a first current-conducting terminal of the first transistor and a second terminal coupled to an output of the amplifier circuit; a feedback circuit connected between the output and the control terminal of the second transistor, wherein the feedback circuit includes a first resistor, a second inductor, and a first capacitor; and an input of the amplifier circuit connected between the first resistor and the second inductor, wherein a second current-conducting terminal of the second transistor is connected to a first ground terminal, and wherein a control terminal of the first transistor is connected to a second ground terminal via a third capacitor.

Amplifiers with feedback circuits

Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

High speed switching radio frequency switches

Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.

RF switches, integrated circuits, and devices with multi-gate field effect transistors and voltage leveling circuits, and methods of their fabrication

Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a pair of the gate structures. A first capacitor is electrically coupled between the channel contact and the source terminal, and a second capacitor is electrically coupled between the channel contact and the drain terminal.

Growing community of inventors

Tempe, AZ, United States of America

Venkata Naga Koushik Malladi