Qualcomm Incorporated

Venkata Biswanath Devarasetty

Nirav Narendra Desai

Sharath Kumar Nagilla

Darshan Kumar Nandanwar

Hithesh Hassan Lepaksha

Lakshmi Narayana Panuku

Deva Sudhir Kumar Pulivendula

Venkatesh Ravipati

Sravan Kumar Ambapuram

Srinivas Turaga

Karthik Rangaraju

Nikhil Kumar Kansal

Nikesh Gupta

Harshit Tiwari

Kumar Kanti Ghosh

Sarbartha Banerjee

Vinay Jain

Akshay Kumar Gupta

Shrikanth Shenoy

Sumit Gemini

Srikanth Gudipudi

Manisha Singh

Systems, methods and computer-readable mediums may be used in portable computing devices (PCDs) for dynamically allocating system resources in a way that prevents or lessens degradation of power and performance KPIs while also avoiding temperature increases in the PCD that can create unpleasant user experiences. A smart resource allocation framework (SRAF) is triggered when a call is received or placed. Once triggered, the SRAF framework monitors a preselected set of state conditions to determine whether or not to place the wireless modem in a modem power-performance (Mod. Pow.-Perf) mode. If it determines that modem is to be placed in the Mod. Pow.-Perf. mode, a Mod. Pow.-Perf. process is performed dynamically allocates system resources and preferably also triggers a thermal framework that performs power reduction in one or more non-modem processing cores.

Smart resource allocation framework for dynamic allocation of system resources in personal computing devices (PCDs) that employ wireless modems

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting a number of cache lines that satisfy an eviction criteria based on a deterministic cache eviction policy in each cache way of a group of cache ways; selecting at least one cache way from the group for collapse, based on its corresponding number of cache lines that satisfy the eviction criteria; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Performance aware partial cache collapse

Aspects of the present disclosure relate to systems and methods for improving performance of a partial cache collapse by a processing device. Certain embodiments provide a method for performing a partial cache collapse procedure, the method including: counting, in each cache way of a group of cache ways, a number of dirty cache lines having dirty bits indicating the cache line has been modified; selecting, from the group, at least one cache way for collapse, based on its corresponding number of dirty cache lines; and performing the partial cache collapse procedure based on the at least one cache way selected from the group for collapse.

Access optimized partial cache collapse

An apparatus sets an operating voltage of a shared power rail in a multi-core electronic device. The apparatus includes a system-on-chip (SoC) having multiple cores with each core in the SoC configured to report an operating status. The apparatus includes an operating state aggregator configured to receive the operating status reported from each core in the SoC and to select the selected operating voltage based on the operating status from each core. A voltage regulator is in communication with the operating state aggregator and a power management integrated circuit (PMIC). The selected operating voltage is then programmed into the (PMIC) to control the shared power rail.

Dynamic voltage selection for a single power rail in a multi-core domain

A method for reducing power in a system is provided according to aspects of the present disclosure. The system includes a chip, and a volatile memory. The method includes entering a sleep state, and exiting the sleep state. Entering the sleep state includes placing the volatile memory in a self-refresh mode, wherein the volatile memory stores one or more binary images and the volatile memory is powered in the sleep state, and collapsing multiple power supply rails on the chip. Exiting the sleep state includes restoring power to the multiple power supply rails on the chip, taking the volatile memory out of the self-refresh mode, and running the one or more binary images on one or more sub-systems on the chip.

Quick energy efficient reboot from ultra-low power mode for a system on a chip

Aspects of the disclosure are directed to DC power management. A sequencer may be configured to execute a first command, wherein the first command is associated with a unique group tag; compare the unique group tag to a master group tag; determine if an interrupt is detected; lock the master group tag to yield a locked master group tag; execute a second command, wherein the second command is associated with the locked master group tag; determine that an end of commands in the locked master group tag is reached and execute a sequence jump through command to put a processor back to a regular power state.

Advanced fall through mechanism for low power sequencers

A method and an apparatus for providing a power grid are provided. The apparatus includes a plurality of memory units comprising at least one SoC memory and at least one cache memory. The apparatus includes a first subsystem coupled to the at least one SoC memory associated with a first power domain. The apparatus further includes a second subsystem coupled to the at least one cache memory associated with a second power domain. The second subsystem may be a CPU subsystem. Because the first power domain sources power from a shared power source, the first power domain may operate at a voltage level that is higher than the operation of memory circuits requires. By moving the at least one cache memory from the first power domain to the second power domain, LDO efficiency loss for components in the first power domain may be reduced.

Power-aware CPU power grid design

Growing community of inventors

Hyderabad Telangana, India

Venkata Biswanath Devarasetty