National Semiconductor Corporation

Agere Systems Inc.

Texas Instruments Corporation

Venkat Raghavan

Andrew Derek Strachan

Arun Kumar Nanda

Nace Rossi

Sheldon D Haynie

In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Schottky diode integrated into LDMOS

A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.

Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance density

An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Data retention in a single poly EPROM cell

A method for integrating a metal-insulator-metal (MIM) capacitor and a thin film resistor in an integrated circuit is provided that includes depositing a first metal layer outwardly of a semiconductor wafer substrate. A portion of the first metal layer forms a bottom plate for a MIM capacitor. A second metal layer is deposited outwardly of the first metal layer. A first portion of the second metal layer forms a top plate for the MIM capacitor and a second portion of the second metal layer forms contact pads for a thin film resistor.

Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding device

A method for forming BiCMOS integrated circuits and structures formed according to the method. After forming doped wells and gate stacks for the CMOS devices and collector and base regions for the bipolar junction transistor, an emitter layer is formed within an emitter window. A dielectric material layer is formed over the emitter layer and remains in place during etching of the emitter layer and removal of the etch mask. The dielectric material layer further remains in place during source/drain implant doping and activation of the implanted source/drain dopants. The dielectric material layer functions as a thermal barrier, to limit out-diffusion of the emitter dopants during the activation step.

Method for forming a bipolar junction transistor and a metal oxide semiconductor field effect transistor

Thermally stable BiCMOS fabrication method and bipolar junction transistors formed according to the method

In a method of forming MIM capacitor structure, a TiW layer is formed and a capacitor mask is used to define areas of the TiW layer that will be sued in the formation of the MIM capacitor. A capacitor mask is then used to expose surface areas of the TiW layer, followed by deposition of a capacitor dielectric layer. A via mask and etch are then performed to provide a contact via to the bottom plate TiW layer. After the via etch, a Ti/TiN liner stack is deposited. The Ti/TiN multilayer stacked film serves as the capacitor top plate as well as the via contact liner film. Next, Tungsten is deposited to fill the vias and a Tungsten planarization step is performed.

Growing community of inventors

Union City, CA, United States of America

Venkat Raghavan