Sun Microsystems, Inc.

Venkat R Podduturi

Yu-Yen Mo

Manoj Gopalan

Peter F Lai

Shyam Sundar

Yet-Ping Pai

Dae Suk Jung

Kong-Fai Woo

Sachin Chopra

Seong Rai Cho

Vishal Chopra

A method for inserting flip-flops in an interconnect is provided such that a cycle time constraint for the interconnect is satisfied. First of all, a flop is inserted at an initial placement at a node along a signal path of the interconnect such that a downstream delay relative to the initial placement of the flop is not greater than the cycle time constraint for the net. Secondly, the initial placement of the flop is optimized such that a delay difference, defined by a downstream delay minus an upstream delay, relative to an optimal placement at a downstream node along the signal path of the net is not greater than zero. The disclosed method can also satisfy the flop stage requirement and/or a minimum number of flops requirement for an interconnect.

Flip-flop insertion method for global interconnect pipelining

A method and system for inserting repeaters at different levels in a processor hierarchy involve tracing a net in a processor circuit followed by inserting repeaters at different locations in the net. The net is a circuit trace of wiring between circuit elements of a circuit, the net being divided into two nets. One net includes internal circuit elements of a processor component and another net includes external circuit elements of a processor component. A repeater solution, which includes inserted repeaters coupled to the internal circuit elements, is instantiated to other processor components. Subsequently, after instantiation of the repeater solution, repeaters are inserted in the nets external to the processor component.

Hierarchical repeater insertion

The present invention describes a method and apparatus for placing flops in a complex circuit design. Initially, the method calculates a physical range for every net that requires a flop, within which the flop can be placed satisfying the timing requirement. After the physical range is defined, the method groups these flops and determines a block where these grouped flops can be placed. Grouping these flops into one block (flop station) can preserve a compact layout for the design. The flops are then connected to appropriate nets.

Aggregation of storage elements into stations and placement of same into an integrated circuit or design

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San Jose, CA, United States of America

Venkat R Podduturi