Freescale Semiconductor,inc.

Motorola Corporation

Venkat Kolagunta

Paul Grudowski

Omar Zia

Da Zhang

Nigel Graeme Cave

Bich-Yen Nguyen

Mariam G Sadaka

Suresh Venkatesan

Edward Outlaw Travis, Jr

Janos Farkas

Ruiqi Tian

Mohammed Rabiul Islam

Vance H Adams

Victor H Vartanian

Rajesh Tiwari

Brian George Anthony

John Mendonca

Abbas Guvenilir

Xiangzheng Bo

Mehul D Shroff

Leo Mathew

Sinan Goktepeli

Voon-Yew Thean

Brian A Winstead

Ted R White

Byoung W Min

Alexander L Barr

Narayanan C Ramani

David C Sing

Jian Feng Chen

Jon D Cheek

Vishal P Trivedi

Konstantin V Loiko

Kurt H Junker

Gregory S Spencer

Tien Ying Luo

Michael A Mendicino

Choh-Fei Yeap

Sangwoo Lim

William J Taylor

Stanley L Filipiak

A method for making a semiconductor device is provided which comprises (a) creating a first mask for the epitaxial growth of features in a semiconductor device, said first mask defining a set of epitaxial tiles (); (b) creating a second mask for defining the active region of the semiconductor device, said second mask defining a set of active tiles (); and (c) using the first and second masks to create a semiconductor device.

Integrated assist features for epitaxial growth

An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.

Process of forming an electronic device including insulating layers having different strains

Electronic device including insulating layers having different strains

A method for forming a semiconductor device on a semiconductor material layer includes forming a gate structure over the semiconductor material layer. The method further includes forming a first nitride spacer adjacent to the gate structure and forming source/drain extensions in the semiconductor material layer. The method further includes forming an oxide liner overlying the gate structure and the source/drain extensions. The method further includes forming a second nitride spacer adjacent to the oxide liner. The method further includes forming source/drain regions in the semiconductor material layer. The method further includes using an etching process that is selective to the oxide liner, removing the second nitride spacer. The method further includes using an etching process that is selective to the first nitride spacer, at least partially removing the oxide liner. The method further includes forming silicide regions overlying the source/drain regions and the gate structure.

Method for making a transistor with a stressor

A method for forming a semiconductor device includes providing a substrate and forming a p-channel device and an n-channel device, each of the p-channel device and the n-channel device comprising a source, a drain, and a gate, the p-channel device having a first sidewall spacer and the n-channel device having a second sidewall spacer. The method further includes forming a liner and forming a tensile stressor layer over the liner and removing a portion of the tensile stressor layer from a region overlying the p-channel device. The method further includes transferring a stress characteristic of an overlying portion of a remaining portion of the tensile stressor layer to a channel of the n-channel device. The method further includes using the remaining portion of the tensile stressor layer as a hard mask, forming a first recess and a second recess adjacent the gate of the p-channel device.

Method of making a semiconductor device using a stressor

An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.

Electronic device including a transistor structure having an active region adjacent to a stressor layer

A semiconductor device has at least two tensile stressor layers that are cured with UV radiation. A second tensile stressor layer is formed after a first stressor layer. In some examples, the tensile stressor layers include silicon nitride and hydrogen. In some examples, the second tensile stressor layer has a greater shrinkage percentage due to the curing than the first tensile stressor layer. In one form, the second tensile stressor layer after the curing exerts a greater tensile stress than the first tensile stressor layer. The tensile stressors layers are utilized to improve carrier mobility in an N-channel transistor and thus enhance transistor performance. In one form a single group of overlying tensile stressor layers is provided with each layer being increasingly thicker and having increasingly more hydrogen prior to being cured. In other embodiments multiple overlying groups are formed, each group having a similar repeating depth and hydrogen profile.

Method of forming a semiconductor device with multiple tensile stressor layers

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and a first epitaxial growth mask set () from the first data set, wherein the first epitaxial growth mask set is derived from the first data set by removing a subset () of the tiles defined by the first data set and incorporating the subset of tiles into the first epitaxial growth mask set; and (c) reconfiguring the first trench CMP mask set to account for the first epitaxial growth mask set, thereby defining a second trench CMP mask set ().

Integrated assist features for epitaxial growth bulk tiles with compensation

An electronic device can have an insulating layer lying between a first semiconductor layer and a base layer. A second semiconductor layer, having a different composition and stress as compared to the first semiconductor layer, can overlie at least a portion of the first semiconductor layer. In one embodiment, a first electronic component can include a first active region that includes a first portion of the first and the second semiconductor layers. A second electronic component can include a second active region that can include a second portion of the first semiconductor layer. Different processes can be used to form the electronic device. In another embodiment, annealing a workpiece can be performed and the stress of at least one of the semiconductor layers can be changed. In a different embodiment, annealing the workpiece can be performed either before or after the formation of the second semiconductor layer.

Process for forming an electronic device including semiconductor layers having different stresses

First and second transistors are formed adjacent to each other. Both transistors have gate sidewall spacers removed. A stressor layer is formed overlying the first and second transistors. Stress in the stressor layer that overlies the first transistor is modified. Stress in the stressor layer that overlies the second transistor is permanently transferred to a channel of the second transistor. The stressor layer is removed except adjacent the gate electrode sidewalls of the first transistor and the second transistor where the stressor layer is used as gate sidewall spacers. Electrical contact to electrodes of the first transistor and the second transistor is made while using the gate sidewall spacers for determining a physical boundary of current electrodes of the first and second transistors. Subsequently formed first and a second stressors are positioned close to transistor channels of the first and second transistors.

Method of making a semiconductor device with a stressor

A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Process of forming an electronic device including a seed layer and a semiconductor layer selectively formed over the seed layer

An electronic device can include a first transistor structure including a first gate electrode surrounded by a first sidewall spacer having a first stress and a second transistor structure including a second gate electrode surrounding a second sidewall spacer having second stress. The first sidewall spacer is an only sidewall spacer surrounding the first gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the first gate electrode and the second sidewall spacer is an only sidewall spacer surrounding the second gate electrode or a closer sidewall spacer as compared to any other sidewall spacer that surrounds the second gate electrode, wherein the first stress has a lower value as compared to the second stress. More than one process can be used to form the electronic device.

Process for forming an electronic device including transistor structures with sidewall spacers

A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Transfer of stress to a layer

A method for making a semiconductor device is provided which comprises (a) creating a first data set () which defines a first set of tiles () for a trench chemical mechanical polishing (CMP) process; (b) deriving a first trench CMP mask set () and at least one epitaxial growth mask set () from the first data set, wherein the at least one epitaxial growth mask set corresponds to tiles () present on first () and second () distinct semiconductor surfaces; (c) reconfiguring the first trench CMP mask set to account for the at least one epitaxial growth mask set, thereby defining a second trench CMP mask set (), wherein the second trench CMP mask set defines a set of trench CMP tiles; and (d) using the second trench CMP mask set to make a semiconductor device.

Integrated assist features for epitaxial growth bulk/SOI hybrid tiles with compensation

Electronic device including a transistor structure having an active region adjacent to a stressor layer and a process for forming the electronic device

Growing community of inventors

Austin, TX, United States of America

Venkat Kolagunta