Intel Corporation

Venkat Iyer

John I Garney

John S Howard

Vui Yong Liew

Michael J Pennell

Mitchell Beck

John Todd West

A Universal Serial Bus repeater is provided, comprising a method and apparatus for detecting a specified data pattern and regenerating or retransmitting the recognized data pattern. In some embodiments, the invention recognizes an end of sync signal, and is operable to retransmit the end of sync signal and the following data that is presumed to be valid as a result of sync recognition. In other embodiments, the invention recognizes and retransmits a properly aligned end of packet signal, the size of which is dependent on detection of whether the end of packet signal is a part of a start of frame packet.

Sync regeneration in a universal serial bus

A bus controller and its associated device drivers are provided to a digital system to operate and control a peripheral bus, including the selective operation of at least a first portion of the peripheral bus in a store-and-forward manner. The device drivers include a number of programming instructions. Upon programmed with the programming instructions, a digital system is enabled to operate the bus controller to facilitate communication with a first bus agent in this first portion. The programming instructions package a number of request packets destined for the first bus agent into a multi-packet package, schedule the multi-packet package to be transmitted in bulk, at a first communication speed, to a first hub in the first portion, for the first hub to buffer the request packets, and then forward the request packets to the first bus agent, on a packet-by-packet basis and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. In one embodiment, the programming instructions further schedule communications destined for a second bus agent of this first portion, for transmission to the first hub, at the first communication speed, for the first hub to repeat the communications for the second bus agent without buffering, at also the first communication speed.

Bus controller and associated device drivers for use to control a peripheral bus having at least one store-and-forward segment

An improved USB connection is disclosed that includes a pair of host parallel resistors connected to the USB connection at the host termination and a pair of peripheral parallel resistors connected to the USB connection at the peripheral termination. During high speed operation, the parallel resistors are switched to ground. Another aspect of the present invention is a voltage pull up apparatus for a USB connection. The apparatus includes a pull down resistor connected to the USB connection, a trickle current source attached to the USB connection, and a boost current source attached to the USB connection.

Dual termination serial data bus with pull-up current source

A parallel bit stuffing method acting on a stream of serial data is disclosed. First, an input data segment is segmented from said stream of serial data. Next, a carryover segment is appended to the input data segment to form an address field. The address field is used to correlate to an output field that includes a stuffed data portion and a carryover segment portion. The carryover segment portion is used in a next cycle as the carryover segment. Finally, the stuffed data portion is output as output data segments.

Parallel bit stuffing for a serial data transfer protocol

A digital system is provided with a bus controller to operate and control a peripheral bus, wherein the bus controller selectively operates at least a first portion of the peripheral bus in a store-and-forward manner. The bus controller facilitates communication with a first bus agent in this first portion by sending a number of request packets destined for the first bus agent to a first hub in the first portion, in an integrated multi-packet form, in bulk, and at a first communication speed. The first hub buffers the request packets, and then forwards the request packets to the first bus agent, on a packet-by-packet basis, and at a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. In one embodiment, the first hub also receives communications destined for a second bus agent of this first portion, from the bus controller at the first communication speed, and repeats the communications for the second bus agent without buffering, at also the first communication speed. In another embodiment, the peripheral bus further includes a second portion, including a second hub that receives communications destined for a third bus agent in this second portion, from the bus controller at the second communication speed, and repeats the communications for the third bus agent without buffering, at also the second communication speed.

Digital system having a peripheral bus structure with at least one store-and-forward segment

An I/O peripheral device is equipped with a first collection of circuitry to enable the I/O peripheral device to provide a store-and-forward manner of operation to a segment of a peripheral bus. The first collection of circuitry includes first buffering circuitry to buffer request packets destined for a first bus agent, received from a bus controller in an integrated multi-packet form, in bulk, and at a first communication speed. Furthermore, the first collection includes control circuitry to forward the request packets separately, in a packet-by-packet basis, to the first bus agent, in a second communication speed. In one embodiment, the second communication speed is slower than the first communication speed. The I/O peripheral device further includes second buffer circuitry to buffer response packets to a request from the first bus agent provided separately, and each at the slower second communication speed. The first control circuitry also facilitates forwarding of the buffered response packets to the bus controller in bulk at the faster first communication speed. In one embodiment, the I/O peripheral device further includes second control circuitry to repeat communications destined for a second bus agent, received from the bus controller at the first communication speed, for the second bus agent, at also the first communication speed. In one embodiment, the I/O peripheral device is a hub.

I/O peripheral device for use in a store-and-forward segment of a peripheral bus

A method and apparatus for generating both a uniform duty cycle clock and a variable duty cycle clock with a single state machine. A single state machine is provided having a series of states through which it transitions when in a first mode. The series of states causes the output of the state machine to be a uniform duty cycle clock signal. The state machine has a second group of states through which it transitions in a second mode. A transition scheme among the second group of states permits the duty cycle of a state machine output clock signal to vary.

Growing community of inventors

Beaverton, OR, United States of America

Venkat Iyer