Fairchild Semiconductor Corporation

Flex Ltd.

Other

Venkat Iyer

Rajeev Dinkar Joshi

Chung-Lin Wu

Dongkai Shangguan

Oseob Jeon

Maria Cristina B Estacio

Cheng Yang

Boon Huan Gooi

Byoung-Ok Lee

Yoonhwa Choi

David Geiger

Elsie Agdon Cabahug

Jonathan Klein

Erwin Victor R Cruz

David Chong

Lay Yeap Lim

Ti Ching Shian

Tan Teik Keng

Shibaek Nam

Romel Nogas Manatad

Jonathan A Noquil

Stephen Martin

Connie Tangpuz

Bo Li

Methods include receiving at least one electronic device including a sensor or an emitter, placing a cover over the sensor or emitter, placing the electronic device, including the cover, into a transfer mold system, encapsulating the electronic device with charge material, and removing a portion of the encapsulating charge material and the cover to expose the sensor or emitter to the environment.

Methods of creating exposed cavities in molded electronic devices

An improved SiP structure includes one or more interposers positioned to form a center cavity into which one or more electronic components can be mounted. The improved SiP structure provides a reduced footprint using the one or more interposers and formed center cavity without the need of laser drilling, exposed molding, and/or double side molding.

System in package with double side mounted board

Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Semiconductor die package and method for making the same

A semiconductor die package capable of being mounted to a motherboard is disclosed. The semiconductor die package includes a substrate, and a first semiconductor die mounted on the substrate, where the first semiconductor die includes a first vertical device comprising a first input region and a first output region at opposite surfaces of the first semiconductor die. The semiconductor die package includes a second semiconductor die mounted on the substrate, where second semiconductor die comprises a second vertical device comprising a second input region and a second output region at opposite surfaces of the second semiconductor die. A substantially planar conductive node clip electrically communicates the first output region in the first semiconductor die and the second input region in the second semiconductor die. The first semiconductor die and the second semiconductor die are between the substrate and the conductive node clip.

Semiconductor die package including multiple dies and a common node structure

A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).

Semiconductor die package using leadframe and clip and method of manufacturing

A semiconductor die package is disclosed. It may include a semiconductor die having a first surface and a second surface, and a leadframe structure. A molding material may be formed around at least a portion of the die and at least a portion of the leadframe structure. A solderable layer may be on the exterior surface of the molding material and the first surface of the semiconductor die.

Method to manufacture a universal footprint for a package with exposed chip

Growing community of inventors

Cupertino, CA, United States of America

Venkat Iyer