Broadcom Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP Pte, Ltd.

Velu Pillai

Vivek Telang

Ali Ghiasi

Magesh Valliappan

Afshin Momtaz

Namik Kocaman

Sundararajan Chidambara

Sundar Chidambara

Wael William Diab

A system side interface of a PHY chip used in conjunction with a 100 GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an 'overclocked' NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Overclocked line rate for communication with PHY Interfaces

A system side interface of a PHY chip used in conjunction with a 100GBASE backplane, sends and receives data using an NRZ signal format, but at a data rate of between about 26.5 Gbps/per lane to 27.2 Gbps/per lane, which is consistent with the PAM 4 signaling protocol. Thus, chip-to-chip communications between a PHY chip and a switch or controller chip can use an 'overclocked' NRZ signaling format, reducing the amount of logic needed, which in turn can reduce signal latency, and reduce the chip area and power consumption required to implement the logic.

Overclocked line rate for communication with PHY interfaces

A system, method and apparatus for multi-lane auto-negotiation over reduced-lane media. Auto-negotiation over an M-lane communication interface can be coordinated with the auto-negotiation over an N-lane communication interface, wherein M&#x3e;N. A recursive-type auto-negotiation process would begin with the M-lane communication interface and be prevented from completing until the auto-negotiation process over the N-lane communication interface completes.

System, method and apparatus for multi-lane auto-negotiation over reduced lane media

Disclosed are various embodiments for in-band management of Ethernet links utilizing a bit-interleaved parity (BIP) block in a transmission frame. According to various embodiments, a bit-interleaved parity error code may be generated for a monitored portion of network data for transmission in a first bit-interleaved parity block. Subsequently, network management data may be encoded in a plurality of bits for transmission in a second bit-interleaved parity block according to a predefined block code, wherein the predefined block code generates the plurality of bits to maintain a DC balance between the bit-interleaved parity error code and the plurality of bits.

Inband management of ethernet links

A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10G/40G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

System and method for increasing input/output speeds in a network switch

An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

Adaptive offset adjustment algorithm

Input/output of network switches and the like are improved by a system including a gearbox, an inverse-gearbox, and a Gigabit Ethernet link coupling them. The gearbox and inverse-gearbox interconnect data streams received through wider lower rate Gigabit Ethernet interfaces through narrower faster rate interfaces. The gearbox is configured to bit-multiplex physical-layer data streams received through input interfaces to generate bit-multiplexed data streams. The inverse-gearbox is configured to demultiplex the multiplexed data streams and to output the recovered data streams through output interfaces. One of the output interfaces is selected for each recovered data stream according to a respective embedded physical-layer data stream identifier.

System and method for bit-multiplexed data streams over multirate gigabit Ethernet

A system and method for increasing input/output speeds in a network switch. A physical layer device is provided that includes a physical coding sublayer that insert data flow identifiers to data flows that are provided to a gearbox. In one embodiment, the gearbox is a 5 to 2 gearbox that can transport various combinations of 10 G/40 G data flows over a narrower interface to a second physical layer device having an inverse gearbox.

Aspects of a method and system for energy efficient networking over a serial communication channel are provided. In this regard, one or more circuits in an Ethernet PHY that communicates over one or more serial communication channels may transmit and/or receive physical layer signals to maintain and/or refresh synchronization and/or training parameters while operating in an energy saving mode. The Ethernet PHY may transition out of the energy saving mode upon transmitting and/or receiving a wake sequence via the serial communication channel(s), where the wake sequence comprises one or more deterministic forward error correction (FEC) block in instances that FEC is utilized for communications via the serial communication channel(s). The one or more circuits in the Ethernet PHY may be operable to perform forward error correction (FEC) functions and one or more of the FEC functions may be disabled while remaining ones of the FEC functions are enabled.

Method and system for energy efficient networking over a serial communication channel based on forward error correction support

According to an example embodiment, an apparatus may include logic. The apparatus may be configured to: determine, based on an error location polynomial, an error location syndrome corresponding to an actual location of a burst error in a data block; select a burst error pattern that is less than or equal to M bits, and having no more than Y consecutive zeros within the burst error, where M is greater than the order of the error location polynomial; determine an error pattern syndrome based on the selected burst error pattern and the error location polynomial; and determine an actual location of the burst error in the data block based on the error location syndrome and the error pattern syndrome.

Growing community of inventors

Austin, TX, United States of America

Velu Pillai