Infineon Technologies Ag

Veit Klee

Uwe Paul Schroeder

Tobias Mono

Roman Knoefler

Sun-Oo Kim

Nirmal Chaudhary

Paul Wensley

Martin Commons

John Pohl

Paul Schroeder

Uwe Paul Schröder

To form a semiconductor device, an insulating layer is formed over a conductive region and a pattern transfer layer is formed over the insulating layer. The pattern transfer layer is patterned in the reverse tone of a layout of recesses to be formed in the insulating layer such that the pattern transfer layer remains over regions where the recesses are to be formed. A mask material is formed over the insulating layer and is aligned with the pattern transfer layer. Remaining portions of the pattern transfer layer are removed and recesses are etched in the insulating layer using the mask material as a mask.

Method of making a contact in a semiconductor device

A method of making a semiconductor device for an integrated circuit chip. An interim gate electrode stack formed includes a top silicon portion patterned from a second silicon layer, a sandwiched oxide portion patterned from an etch stop oxide layer, and a bottom silicon portion patterned from a first silicon layer formed on a gate dielectric layer over a substrate. Etching the second silicon layer is stopped at the etch stop oxide layer. A spacer structure is formed about the interim gate electrode stack, and then the top silicon portion and the sandwiched oxide portion are removed. The spacer structure height may be reduced. A metal layer is formed over the bottom silicon portion of the interim gate electrode stack and over source and drain regions of the substrate, all of which are silicided at the same time to form a fully silicided (FUSI) gate electrode and silicided source and drain regions.

Method of making fully silicided gate electrode

An alternating phase shift mask ( ) and method of manufacturing thereof including assist edges ( ) and ( ) surrounding a main phase edge ( ). Assist edges ( ) and ( ) improve the resolution of the alternating phase shift mask ( ), thus enabling the patterning of smaller size features on a semiconductor wafer.

Resolution enhancement for alternating phase shift masks

A method of providing shallow trench ( ) isolation for a semiconductor wafer ( ). Trenches ( ) are formed within a first semiconductor material ( ) and a pad nitride ( ), leaving a portion of first semiconductor material ( ) and pad nitride ( ) in a region between the trenches ( ). A second semiconductor material ( ) is deposited over the trenches ( ) to fill the trenches ( ) to a height below the first semiconductor material ( ) top surface. A first insulator ( ) is selectively formed over the second semiconductor material ( ). The pad nitride ( ) and a portion of the first semiconductor material ( ) between the trenches ( ) are removed to isolate element regions of the wafer ( ) and form straps ( ) having a low resistance.

Strap resistance using selective oxidation to cap DT poly before STI etch

A nitride hard mask ( ) is used to isolate active areas of a DRAM cell. The shallow trench isolation (STI) method includes forming memory cells comprising deep trenches ( ) on a semiconductor wafer ( ). The memory cell deep trenches ( ) are separated from active areas ( ) by a region of substrate ( ). A nitride hard mask ( ) is formed over the semiconductor wafer ( ). The wafer ( ) is patterned with the nitride hard mask ( ), and the wafer ( ) is etched to remove the region of substrate ( ) between the deep trenches and active areas to provide shallow trench isolation. An etch chemistry selective to the nitride hard mask ( ) is used.

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Pleasant Valley, NY, United States of America

Veit Klee