Advanced Micro Devices Corporation

Mosel Vitelic Corporation

Agate Logic, Inc.

Aplus Flash Technology, Inc.

Promos Technologies, Inc

Microsoft Technology Licensing, LLC

Amic Technology Corporation

Cswitch Corporation

Agale Logic, Inc.

Agata Logic Inc.

Vei-Han Chan

Sameer S Haddad

Antonietta Oliva

Louis Charles Kordus, Ii

Peter Wung Lee

Hung-Sheng Chen

Chia-Shun Hsiao

Chi K Chang

Chung Wai Leung

Narbeh Derharcobian

Mark T Ramsbey

Yu Nan Sun

Timothy J Thurgate

Hsing Ti Tuan

Fu-Chang Hsu

Hsing-Ya Tsao

Scott D Luning

Colin Stewart Bill

Nicholas H Tripsas

Narbeh Derhacobian

Daniel Sobek

Zhanping Xu

Ching-Hwa Chen

Janet S Wang

Thomas E Stewart

Mark W Randolph

Ravi S Sunkavalli

Ravi Prakash Gutala

Li-Chun Li

Yi Ding

David K Y Liu

Zhong Dong

Chuck Jang

Kou-Su Chen

Colin Neal Murphy

Wing Han Leung

John Chen

Cyrus Soli Bamji

Jin-Ho Kim

Onur Can Akkaya

Scott Luning

Swati Mehta

Jonathan S Su

Chunchieh Huang

George Kovall

Tamer Elkhatib

Sunil Prakash Acharya

William Qian

Jonathan Shi-Chang Su

Mei-Hua Chung

Chung-Wai Leung

Raymond Yu

Thomas Stewart, Jr

Louis Charles Kordus

Steven Ming Yang

A three-dimensional camera having a micro lens (ML) array configured with variable ML height and variable ML shift is described herein. The ML array includes micro lens that are configured to direct backscattered light that is transmitted through an image lens into corresponding pixels. Heights of individual micro lenses within the ML array vary according to image height. For example, the height of micro lenses at the center of the ML array, near the axis of the image lens, may be relatively larger than the height of other micro lenses toward the perimeter of the ML array. Furthermore, the shift of individual micro lenses with respect to corresponding pixels may also vary according to the image height. For example, the shift of micro lenses at the center of the ML array may be relatively smaller than the shift of the other micro lenses toward the perimeter of the ML array.

Micro lens sensor having micro lens heights that vary based on image height

A three-dimensional time-of-flight (TOF) RGB-IR image sensor is provided, including a signal generator configured to generate a modulated electrical signal. The three-dimensional TOF RGB-IR image sensor may further include a light-emitting diode (LED) configured to receive the modulated electrical signal and emit modulated light. The three-dimensional TOF RGB-IR image sensor may further include a TOF sensor integrated circuit configured to receive light at the light-receiving surface and generate a photoelectrical signal based on the received light. The received light may include ambient light and reflected modulated light. The three-dimensional TOF RGB-IR image sensor may further include a filter array located on the light-receiving surface of the TOF sensor integrated circuit. The filter array may include a plurality of pixels, each pixel including an infrared-transmitting bandpass filter and one or more visible-light-transmitting bandpass filters located adjacent to the infrared-transmitting bandpass filter.

Time-of-flight RGB-IR image sensor

A three-dimensional time-of-flight (3D TOF) camera having a micro lens (ML) array configured with variable ML height and variable ML shift. The ML array includes micro lens that are configured to direct backscattered light that is transmitted through an image lens into corresponding pixels. Heights of individual micro lenses within the ML array vary according to image height. For example, the height of micro lenses at the center of the ML array, near the axis of the image lens, may be relatively larger than the height of other micro lenses toward the perimeter of the ML array. Furthermore, the shift of individual micro lenses with respect to corresponding pixels may also vary according to the image height. For example, the shift of micro lenses at the center of the ML array may be relatively smaller than the shift of the other micro lenses toward the perimeter of the ML array.

Micro lens time-of-flight sensor having micro lens heights that vary based on image height

A CMOS time-of-flight image sensor must be robust to interface traps and fixed charges which may be present due to fabrication and which may cause an undesired induced electric field in the silicon substrate. This undesired induced electrical field is reduced by introducing a hydrogen-enriched dielectric material. Further remedial techniques can include applying ultraviolet light and/or performing a plasma treatment. Another possible approach adds a passivation doping layer at a top of the detector as a shield against the undesired induced electric field. One or more of the above techniques can be used to prevent any unstable behavior of the time-of-flight sensor.

CMOS image sensor with a reduced likelihood of an induced electric field in the epitaxial layer

Phase change devices, particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. Structure allows application in which an electrical connection can be created between two active terminals, with control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals, allowing use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. Programming control can be placed outside of main signal path through the phase change device, reducing impact of associated capacitance and resistance of the device.

Multi-terminal phase change devices

A programmable logic device (PLD) provides voltage identification (VID) codes to a voltage regulator module having VID capabilities. The voltage regulator module generates supply Vdd and/or body bias Vbb voltages according to a selected VID code. The value of the supply Vdd and/or body bias Vbb voltages generated and applied to the PLD determine the operating characteristics of the PLD. The VID codes can be provided and stored in various ways: by an addressable lookup table (LUT) integrated with the PLD, by a memory device in which the VID codes are transferred from an external memory. The VID codes may also be self-generated by auto-detect circuitry integrated with the PLD. The ability to select a particular VID code for each individual PLD allows the user to optimize operational characteristics of the device to satisfy power and/or performance requirements.

Field-programmable gate array having voltage identification capability

Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.

Impedance matching and trimming apparatuses and methods using programmable resistance devices. According to one exemplary embodiment, the impedance matching circuit includes a programmable resistance element, a comparator, a resistor divider having a common node coupled to a first input of the comparator, and an impedance element control circuit coupled between an output of the comparator and the programmable resistance element. The programmable resistance element includes one or more programmable resistance devices (PRDs). Programmed resistances of the programmable resistance element combine with the resistance of an external reference resistor to provide an impedance matched termination. A change in the resistance of the termination impedance causes a change in the output of the comparator. The impedance element control circuit responds to changes in the output of the comparator by providing one or more program control output signals, which control the resistance values of one or more of the PRDs, thereby maintaining an impedance matched termination.

Impedance matching and trimming apparatuses and methods using programmable resistance devices

Method for selectively establishing an electrical connection in a multi-terminal phase change device

Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.

Method of forming ONO-type sidewall with reduced bird's beak

Reconfigurable electronic structures and circuits using programmable, non-volatile memory elements. The programmable, non-volatile memory elements may perform the functions of storage and/or a switch to produce components such as crossbars, multiplexers, look-up tables (LUTs) and other logic circuits used in programmable logic structures (e.g., (FPGAs)). The programmable, non-volatile memory elements comprise one or more structures based on Phase Change Memory, Programmable Metallization, Carbon Nano-Electromechanical (CNT-NEM), or Metal Nano-Electromechanical device technologies.

Reconfigurable logic structures

Apparatus and methods for reducing single-event upsets (SEUs) in latch-based circuitry (e.g., static random access memory (SRAM) cells) and other digital circuitry. According to an exemplary embodiment, a latch-based circuit includes a radiation-hardened latch having first and second cross-coupled inverters and first and second programmable resistance devices (PRDs). The first PRD is coupled between the output of the first inverter and the input of the second inverter. The second PRD is coupled between the output of the second inverter and the input of the first inverter. The PRDs may be programmed to low or high-resistance states. When SET to a low-resistance state, the latch of the latch-based circuitry may be accessed to read the current logic state stored by the latch or to write a new logic state into the latch. When RESET to a high-resistance state, the latch is in a radiation-hard state, thereby preventing the latch from generating SEUs.

SEU hardened latches and memory cells using programmable resistance devices

Methods for fabricating multi-terminal phase change devices

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San Jose, CA, United States of America

Vei-Han Chan