International Business Machines Corporation

Imec Vzw

Veeresh Vidyadhar Deshpande

Lukas Czornomaz

Jean Fompeyrine

Vladimir Djara

Stefan Abel

Abu Sebastian

Daniele Caimi

Pouya Hashemi

Wabe W Koelmans

Vara Sudananda Prasad Jonnalagadda

Oleg Gluschenkov

Heike E Riel

Heinz Schmid

Howard Smith Landis

Daniel A Corliss

Sadanand Vinayak Deshpande

Mattias B Borg

Lukas Czomomaz

Arun Sankar Mampazhy

Neelima Mandloi

Sivarama Krishnan

Ute Drechsler

Stefan Filipp

Andreas Fuhrer

Marc Ganzhorn

Bertrand Parvais

Andreas Kuhlmann

An integrated optical circuit for an optical neural network is provided. The integrated optical circuit is configured to process a phase-encoded optical input signal and to provide a phase-encoded output signal depending on the phase-encoded optical input signal. The phase-encoded output signal emulates a synapse functionality with respect to the phase-encoded optical input signal. A related method and a related design structure are further provided.

Optical synapse

A method for forming a heterojunction bipolar transistor is provided. The method includes (a) forming a doped region in a group IV semiconductor layer of a substrate; (b) forming an epitaxially grown III-V semiconductor body on a surface portion of the doped region, the body extending from the surface portion and protruding vertically above the doped region, wherein the doped region and the body forms a first sub-collector part and a second sub-collector part, respectively; and (c) forming an epitaxially grown III-V semiconductor layer stack on the body, the layer stack comprising a collector, a base and an emitter. There is further provided a heterojunction bipolar transistor device.

Method for forming a heterojunction bipolar transistor and a heterojunction bipolar transistor device

An integrated optical circuit for an optical neural network is provided. The optical circuit is configured to process a plurality of phase-encoded optical input signals and to provide a phase-encoded optical output signal depending on the phase-encoded optical input signals. The phase-encoded optical output signal emulates a neuron functionality with respect to the plurality of phase-encoded optical input signals. Such an embodied optical circuit uses the phase to encode information in the optical domain. A related method and a related design structure are further provided.

Optical neuron

A method for hardware-implemented training of a feedforward artificial neural network is provided. The method comprises: generating a first output signal by processing an input signal with the network, wherein a cost quantity assumes a first cost value; measuring the first cost value; defining a group of at least one synaptic weight of the network for variation; varying each weight of the group by a predefined weight difference; after the variation, generating a second output signal from the input signal to measure a second cost value; comparing the first and second cost values; and determining, based on the comparison, a desired weight change for each weight of the group such that the cost function does not increase if the respective desired weight changes are added to the weights of the group. The desired weight change is based on the weight difference times &#x2212;1, 0, or +1.

Hardware-implemented training of an artificial neural network

A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer is arranged between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.

Tunable resistive element

A neuromorphic network includes a first node configured to transmit a first optical signal and a second node configured to transmit a second optical signal. A waveguide optically connects the first node to the second node. An integrated optical synapse is located on the waveguide between the first node and the second node, the optical synapse configured to change an optical property based on the first optical signal and the second optical signal such that if a correlation between the first optical signal and the second optical signal is strong, the optical connection between the first node and the second node is increased and if the correlation between the first optical signal and the second optical signal is weak, the optical connection between the first node and the second node is decreased.

Optical synapse for neuromorphic networks

Embodiments are directed to a superconducting microwave circuit. The circuit includes a substrate and two electrodes. The latter form an electrode pair dimensioned so as to support an electromagnetic field, which allows the circuit to be operated in the microwave domain. The substrate exhibits a raised portion, which includes a top surface and two lateral surfaces. The top surface connects the two lateral surfaces, which show respective undercuts (on the lateral sides of the raised portions). Each of the electrodes includes a structure that includes a potentially superconducting material. Two protruding structures are accordingly formed, which are shaped complementarily to the respective undercuts. This way, the shaped structure of each of the electrodes protrudes toward the other one of the electrodes of the pair.

Buried electrode geometry for lowering surface losses in superconducting microwave circuits

A method of fabrication of an array of optoelectronic structures includes first providing a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells includes an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portions that coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

Array of optoelectronic structures and fabrication thereof

A tunable resistive element, comprising a first terminal, a second terminal, a dielectric layer and an intercalation layer. The dielectric layer and the intercalation layer are arranged in series between the first terminal and the second terminal. The dielectric layer is configured to form conductive filaments of oxygen vacancies on application of an electric field. The intercalation layer is configured to undergo a topotactic transition comprising an oxygen intercalation in combination with a change in the resistivity of the intercalation layer. A related memory device and a related neuromorphic network comprise resistive memory elements as memory cells and synapses respectively and a corresponding design structure.

The invention relates to a method comprising providing a substrate with a channel layer, forming a gate stack structure on the channel layer and forming a raised source and a raised drain on the channel layer. The method further comprises depositing in a non-conformal way an oxide layer above the gate stack structure, the raised source and the raised drain. A first void above the raised source and a second void above the raised drain gate are created adjacent to vertical edges of the gate stack structure. The method further comprises etching the oxide layer for a predefined etching time, thereby removing the oxide layer above the raised source and the raised drain, while keeping it at least partly on the channel layer. Contacts are formed to the raised source and the raised drain. The invention also concerns a corresponding computer program product.

Fabricating contacts of a CMOS structure

Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.

Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions

A reservoir computing neuromorphic network includes an input layer comprising one or more input nodes, a reservoir layer comprising a plurality of reservoir nodes, and an output layer comprising one or more output nodes. A portion of at least one of the input layer, the reservoir layer, and the output layer includes an optically tunable material.

Tunable optical neuromorphic network

The invention relates to a method for forming a field effect transistor. The method comprises providing a substrate with a channel layer, forming a gate stack structure on the channel layer, forming first sidewall spacers, forming a raised source and a raised drain on the channel layer and forming second sidewall spacers above the raised source and the raised drain. The method further includes depositing in a an insulating dielectric layer above the gate stack structure, the first sidewall spacers and the second sidewall spacers, planarization of the insulating dielectric layer and selectively etching the second sidewall spacers. Thereby contact cavities are created on the raised source and the raised drain. The method further includes forming a source contact and a drain contact by filling the contact cavities. The invention also concerns a corresponding computer program product.

Fabricating raised source drain contacts of a CMOS structure

The invention relates to a method for fabricating a semiconductor circuit comprising providing a semiconductor substrate; fabricating a first semiconductor device comprising a first semiconductor material on the substrate and forming an insulating layer comprising a cavity structure on the first semiconductor device. The cavity structure comprises at least one growth channel and the growth channel connects a crystalline seed surface of the first semiconductor device with an opening. Further steps include growing via the opening from the seed surface a semiconductor filling structure comprising a second semiconductor material different from the first semiconductor material in the growth channel; forming a semiconductor starting structure for a second semiconductor device from the filling structure; and fabricating a second semiconductor device comprising the starting structure. The invention is notably also directed to corresponding semiconductor circuits.

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Zurich, Switzerland

Veeresh Vidyadhar Deshpande