Pdf Solutions, Incorporated

Pdf Acquisition Corp.

Veerbhan Kheterpal

Lawrence Thomas Pileggi

Dipti Motiani

Vyacheslav Rovner

Matthew Moe

Thiago G Hersan

The present invention provides in one aspect a method of defining a logic cell library composed of complex functions and simple functions, with some of the complex functions obtained from identifying logic function patterns. In another aspect the present invention provides a method of designing a representation of an integrated circuit that uses complex functions and simple functions, with the complex functions including a plurality of non-standard complex Boolean logic functions that are determined to collectively provide for logic pattern minimization.

Method for the definition of a library of application-domain-specific logic cells

A method and system is described for mapping a system-level description of an integrated system directly to a technology-specific set of logic cells that are comprised primarily of large complex cells (bricks). The invention is based on applying aggressive Boolean operations that would be of impractical runtime complexity for a large library, but are applicable for the targeted brick libraries which typically contain a small number of complex cells, along with a much smaller number of simple cells. This invention is modular such that it can be applied in the context of incremental netlist optimization as well as optimization during physical synthesis.

Method and system for mapping a boolean logic network to a limited set of application-domain specific logic cells

A method and system are described to group logic terms at a higher level of abstraction than that found using standard cells to implement the logic functions using a reduced number of transistors, and to reduce the total number of unique geometry patterns needed to create the integrated circuit implementation. By grouping the logic functions in terms of a larger number of literals (logic variable inputs), the functions can be implemented in terms of a number of transistors that is often less and no more than equal to that which is required for implementing the same function with a number of logic primitives, or simpler standard logic cells. The optimized transistor level designs are further optimized and physically constructed to reduce the total number of unique geometry patterns required to implement the integrated circuit.

Method and system for grouping logic in an integrated circuit design to minimize number of transistors and number of unique geometry patterns

Method for mapping a Boolean logic network to a limited set of application-domain specific logic cells

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Sunnyvale, CA, United States of America

Veerbhan Kheterpal