Qualcomm Incorporated

Veerabhadra Rao Boda

Sharad Kumar Gupta

Mukund Narasimhan

Rahul Sahu

Rakesh Kumar Sinha

Pradeep Raj

Shiba Narayan Mohanty

Adithya Bhaskaran

Akshdeepika

Systems and methods for propagating control signals in memories are described. One implementation includes a plurality of logic gates and a latch coupled between a control signal input and a delay line. The latch may store the value of the control signal before the control signal floats, thereby reducing the risk of incorrect signal propagation. Furthermore, the implementation may also include a clamp signal that isolates the plurality of logic gates before the control signal floats and continues to isolate the plurality of logic gates until after the control signal returns to either a digital one or a digital zero. The clamp signal may reduce leakage by disconnecting transistors within the logic gates from their power supply.

Systems and methods for control signal latching in memories

A memory is provided that includes a negative bit line boost circuit for boosting a discharged bit line to a negative voltage during a negative bit line boost period for a write operation to a selected column in the memory. The memory also includes a core voltage control circuit configured to float a core power supply voltage for the selected column during the negative bit line boost period.

SRAM write yield enhancement with pull-up strength modulation

A write precharge period for a pseudo-dual-port memory is initiated by an edge (rising or falling) of a read precharge signal. The same edge type (rising or falling) of a write precharge signal signals the end of the write precharge period.

Bitline precharge control and tracking scheme providing increased memory cycle speed for pseudo-dual-port memories

A memory is provided in which the word line assertion during a write operation is delayed until the discharge of a dummy bit line is detected.

Memory with a word line assertion delayed by a bit line discharge for write operations with improved write time and reduced write power

A method and an apparatus for generating an internal memory clock are provided. The apparatus includes a pulse generator configured to receive a first clock signal in a first power domain and initiate a second clock signal in a second power domain in response to the first clock signal. The first power domain provides a first voltage for logic operations and the second power domain provides a second voltage for memory operations. The apparatus includes a tracking circuit configured to generate a reset signal based on a voltage level of the first power domain. The reset signal may be configured to reset the pulse generator in the first power domain. The apparatus may further include a latch configured to receive the second clock signal in the second power domain.

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East Godavari, India

Veerabhadra Rao Boda