Samsung Electronics Co., Ltd.

Ved Prakash

Manish Chandra Joshi

Lava Kumar Pulluru

Poornima Venkatasubramanian

Pushp Khatter

Jinesh Parameshwaran Nair

Atanu Guchhait

Dae-Ryong Lee

Anurag Kumar

Ranjit Kumar

Surendra Deshmukh

A write assist circuit includes a first power control circuit and second power control circuit, each comprising a first switch and second switch. The first switch of first power control circuit has first drive strength and is configured to be controlled by a column select line, a power control line, a first bit line, and a power supply. The first switch of the second power control circuit has the first drive strength and is configured to be controlled by the column select line, the power control line, a second bit line, and the power supply. The second switch has a second drive strength and is configured to be controlled by the power control line. The first switches are configured to be controlled using input data on first- and second-bit line, respectively, for altering power supply to first inverter and second inverter of SRAM bitcell.

Write assist circuit for static random-access memory (SRAM)

A memory device includes at least one bitcell; read circuitry coupled to the at least one bitcell; and screening circuitry coupled to the read circuitry, wherein the screening circuitry includes a master slave flip-flop configured to store an output of the at least one bitcell during a read operation of the memory device, wherein the master slave flip-flop includes a master latch and a slave latch; and a DOUT window controller coupled to the master slave flip-flop and configured to generate and control a master clock signal for the master latch to determine if the at least one bitcell is a weak bitcell; and generate and control a slave clock signal for the slave latch to enable toggling of the output of the at least one bitcell during a transparent window between the master clock signal and the slave clock signal.

Methods and systems for managing read operation of memory device with single ended read path

The present disclosure provides a method of selecting a plurality of sets of beam pairs in a wireless communication system. The method includes estimating, by a receiver, channels associated with a plurality of transmit ports for each receive port of a plurality of receive ports; and determining, by the receiver, the plurality of sets of the beam pairs including transmit beam and receive beam using: an average power level at each receive port for at least one transmit port based on the estimated channel associated between the beam pairs, a set of first power matrices, wherein each first power matrix, from the set of first power matrices, comprises at least one transmit port, beam ID pairs including transmit beam ID and receive beam ID associated with each receive port, wherein the set of first power matrices is formed based on the average power level at each of the receive port, and a second capacity matrix formed based on capacity maximization obtained from the set of first power matrices, wherein the plurality of sets of the beam pairs associated with each of the transmit port and receive port is selected from the second capacity matrix.

Method of selecting plurality of sets of optimal beam pairs in wireless communication system

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Karnataka, India

Ved Prakash