Altera Corporation

Altera Toronto Co.

Other

University of Toronto

Vaughn Betz

David Lewis

Andy Louie Lee

Paul Leventis

Ryan Fung

Christopher F Lane

Jordan Swartz

Cameron R McClintock

David Neto

Vadim Gouterman

Richard G Cliff

Srinivas T Reddy

Brian D Johnson

Bruce B Pedersen

Chris Wysocki

David Wolk Mendel

Stephen D Brown

Terry Borer

Ketan Padalia

Alexander Marquardt

Mark Bourgeault

Jonathan Scott Rose

Caroline Pantofaru

James G Schleicher

Henry Kim

Vikram Santurkar

Meghal Varia

Gabriel Quan

Tim Michael Vanderhoek

Chris Lane

Gary Lai

Thomas Yau-Tsun Wong

Michael David Hutton

Gregg William Baeckler

Irfan Rahim

David Edward Jefferson

Deshanand Pratap Singh

Peter John McElheny

David Karchmer

Alan Louis Herrmann

David Samuel Goldman

Kevin Chan

Yow-Juang W Liu

Chris Sanford

Jennifer Farrugia

William Chow

Jeffrey T Watt

Philip Pan

Jinyong Yuan

Srinivas Perisetty

Ninh D Ngo

Babette Van Antwerpen

David Cashman

Richard Yuan

Caroline Rebecca Pantofaru

Marcel A LeBlanc

Michael Chan

Mike Hutton

Ian Chesal

Kimberly Anne Bozman

Yaron Kretchmer

Boris Ratchev

Sarathy Sribhashyam

Timothy Vanderhoek

Yaska Sankar

Russell George Tessier

Thiagaraja Golpalsamy

Olivier Trescases

David Galloway

Triet M Nguyen

Andrew Leaver

Bruce B Pederson

David Ian M Milton

Changsong Zhang

Jason Govig

Zahir Parpia

Elias Ahmed

Adrian Ludwin

Jason Peters

Peter Mcelheny

Shuze Zhao

Ibrahim Ahmed Ibrahim

Ibrahim Ahmed

Kimberley Anne Bozman

A method for designing a system to be implemented on a target device includes generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing its corresponding net. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

Method and apparatus for performing parallel routing using a multi-threaded routing procedure

Modern FPGAs operate at a core voltage around 1V and therefore even small voltage fluctuations can lead to timing violations and logic errors. The Power Delivery Network (PDN) between a power supply and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. The present disclosure describes two techniques for characterization of the PDN: 1) to extract the DC resistance in the power delivery path, and 2) to identify the high impedance frequency band(s) in the PDN. An embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc-dc converter. A self-calibrated Carry-Chain based ADC (CC-ADC) is used for high-speed sampling of the core voltage. By modifying the PDN based on the extracted results, the voltage operating range and reliability of a crossbar application may be greatly extended.

Characterization of power delivery network in field programmable gate arrays or digital integrated circuits

A method for processing signals in a system includes deriving a signal activity for a signal from a timing requirement assignment for the signal.

Method and apparatus for deriving signal activities for power analysis and optimization

A method for designing a system on a target device includes assigning resources on the target device to static logic modules and partial reconfigurable (PR) modules in the system. The instances of one of the PR modules are placed and routed in parallel utilizing resources from those that are assigned. Other embodiments are also disclosed.

Method and apparatus for placing and routing partial reconfiguration modules

A method for designing a system to be implemented on a target device, the method including generating bounding boxes on the target device for nets in the system where a bounding box identifies routing resources available for routing a corresponding net in the bounding box. The nets in the system are assigned to a plurality of threads to be routed. The threads are executed so that a plurality of the nets are routed in parallel within their corresponding bounding box.

A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices

A system for parallelizing software in computer-aided design (CAD) software for circuit design includes a computer. The computer is configured to form or optimize a plurality of clusters in parallel. Each cluster in the plurality of clusters includes a set of nodes in a netlist in a design. The computer is configured to determine placements for blocks in a netlist in parallel, based on iterative improvement, partitioning, or analytic techniques.

Apparatus and associated methods for parallelizing clustering and placement

A method for designing a system on a programmable logic device (PLD) is disclosed. Routing resources are selected for a user specified signal on the PLD in response to user specified routing constraints. Routing resources are selected for a non-user specified signal on the PLD without utilizing the user specified routing constraints.

Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device

A method for designing a system on a target device using an electronic design automation (EDA) tool including identifying synchronizer chains in a system design using timing relationships. According to one embodiment of the present invention, the method includes conveniently reporting system reliability considering synchronization, and automatically protecting and optimizing synchronizer chains to improve system robustness.

Method and apparatus for protecting, optimizing, and reporting synchronizers

Logical memories and other logic functions specified in designs are mapped to power-optimized implementations using physical memories and other device resources. A logical memory may be automatically mapped to numerous potential physical implementations. Power consumption is estimated for each potential physical implementation to select the physical implementation providing the best performance with respect to power consumption and any other design constraints. Potential physical implementations can suppress clock transitions via clock enable inputs when embedded memory is not accessed. Read-enable and write-enable signals can be converted to functionally equivalent clock enable signals. Clock enable signals can be created to deactivate unused memory access ports and to deactivate embedded memory blocks during don't-care conditions. Potential physical implementations can slice logical memory into two or more embedded memory blocks to minimize power consumption.

Power-aware RAM processing

In accordance with one aspect of the invention, a hole is formed within an LE array of a PLD by interrupting the LE array base signal routing architecture such that a hole is left for IP function block to be incorporated. An interface region is provided for interfacing the remaining LE array base signal routing architecture to the IP function block.

PLD architecture for flexible placement of IP function blocks

Growing community of inventors

Toronto, Canada

Vaughn Betz