Intel Corporation

Vasudevan Srinivasan

Krishnakanth Venkata Sistla

Ankush Varma

Nikhil Gupta

James G Hermerding, Ii

Barnes Cooper

Guy M Therien

Chris MacNamara

John Joseph Browne

Eugene Gorbatov

Katalin Klara Bartfai-Walcott

Tawfik M Rahal-Arabi

Arkadiusz Berent

Mark P Baldwin

Vasuki Chilukuri

Bartosz Gotowalski

Vivek Garg

Ian M Steiner

Nagasubramanian Gurumoorthy

Venkatesh Ramamurthy

Jorge Pedro Rodriguez

Corey D Gough

William Johnson Bowhill

Ripan Das

Sujal A Vora

David P Lerner

Joseph M Sullivan

Sanjeev N Trika

Jeremy J Shrall

Ryan Donovan Wells

David W Browning

Eric DiStefano

Alexander Uan-Zo-Li

Neil W Songer

Andrew D Henroid

Jeanna N Matthews

Michael K Eschmann

Venkatesh Ramani

Eliezer Weissmann

Stephen H Gunther

Dorit Shapira

Mariusz Oriol

Philip R Lehwalder

Gang Ji

Vinila Rose

Nilanjan Palit

Abhinav Karhu

Justyna Chilczuk

Mohan J Kumar

Martin Guy Dixon

Murugasamy K Nachimuthu

Don J Nguyen

Michael Glik

Ulf Hanebutte

Stephen T Palermo

Lokpraveen B Mosur

Edwin Verplanke

Jonathan M Eastep

Srihari Makineni

Tomasz Kantecki

Sandeep Ahuja

Federico Ardanaz

Andy Keates

David Birnbaum

Scott P Bobholz

Shrikant M Shah

Christopher MacNamara

Daniel G Borkowski

David Hunt

Haifeng Gong

David T Mayo

Chinmay Ashok

Abhishek Khade

David Novick

Patrick K Leung

Naresh K Sehgal

Ofir Artstain

Susumu Arai

Sarita Maini

Milan Milenkovic

Scott J Cape

Asma Al-Rawi

Avinash P Chakravarthy

Roi Sadan

Hames Hermerding, Ii

Ramya Subramanian

Steven H Gunther

Anatoly Burakov

Bryan T Butters

Antonio J Hasbun Marin

Atanas K Iwanow

Lorie Wigle

Jason Kennedy

A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

Configuration of base clock frequency of processor based on usage parameters

Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

Techniques for restricted deployment of targeted processor firmware updates

Embodiments are generally directed apparatuses, methods, techniques and so forth determine an access level of operation based on an indication received via one or more network links from a pod management controller, and enable or disable a firmware update capability for a firmware device based on the access level of operation, the firmware update capability to change firmware for the firmware device. Embodiments may also include determining one or more configuration settings of a plurality of configuration settings to enable for configuration based on the access level of operation, and enable configuration of the one or more configuration settings.

Techniques to control system updates and configuration changes via the cloud

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement software defined silicon feature licensing are disclosed. Example licensor systems disclosed herein includes a third party verifier to verify one or more credentials included in a request to become an authorized delegated licensor, the request received from a third party. Disclosed example licensor systems also include a feature identifier to identify a feature of a silicon structure which the third party is to be granted the authority to license. Disclosed example licensor systems further include a configuration installation code generator to generate feature configuration installation code, the feature configuration installation code to be used by the third party to generate at least a portion of the license, the portion of the license to be used by a licensee to configure the silicon structure to access the licensed feature, and contents of the feature configuration installation code encrypted to prevent access by the authorized delegated licensor.

Software defined silicon feature licensing

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example non-transitory computer readable medium includes instructions to cause one or more processors to at least generate a first stock keeping unit, associate the first stock keeping unit with a semiconductor device, the first stock keeping unit associated with a first set of features to be provided by the semiconductor device, command the semiconductor device to activate a feature not included in the first set of features to cause the semiconductor device to provide a second set of features, generate a second stock keeping unit for the semiconductor device, and associate the second stock keeping unit with the semiconductor device and the second set of features to be provided by the semiconductor device.

Device enhancements for software defined silicon implementations

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores; one or more peripheral component interconnects to couple the plurality of cores to memory, and in response to a core configuration command to deactivate a core of the plurality of cores, a region within the memory is updated with an indication of deactivation of the core.

Apparatus and method for dynamic control of microprocessor configuration

Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.

Edge server CPU with dynamic deterministic scaling

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to provide device enhancements for software defined silicon implementations are disclosed. Example apparatus disclosed herein include a request interface to receive a request for a timestamp. Disclosed example apparatus also include a property checker to determine a first value of an electrical property of a feature embedded in a silicon product, the feature having electrical properties that change over time. Disclosed example apparatus further include a relative time determiner to calculate a relative time between the request and a previous event based on the first value of the electrical property and a second value of the electrical property, the second value of the electrical property associated with the previous event.

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) for software defined silicon security are disclosed. Example apparatus include a trusted agent determiner to (i) determine respective reputation scores associated with a plurality of agents in a mesh network, the plurality of agents associated with a plurality of semiconductor devices, respective ones of the semiconductor devices including circuitry configurable to provide one or more features, and (ii) select, based on the respective reputation scores, a first agent from the plurality of the agents to transmit a request to activate or deactivate at least one of the one or more features. Example apparatus also include an agent interface to, in response to the request, broadcast an activation or deactivation of the least one of the one or more features to the mesh network to cause the trusted agent determiner to update the reputation score of the first agent.

Systems, methods, and apparatus for software defined silicon security

Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement and manage software defined silicon products are disclosed. Example semiconductor devices disclosed herein include circuitry configurable to provide one or more features. Disclosed example semiconductor devices also include a license processor to activate or deactivate at least one of the one or more features based on a license received via a network from a first remote enterprise system. Disclosed example semiconductor devices further include an analytics engine to report telemetry data associated with operation of the semiconductor device to at least one of the first remote enterprise system or a second remote enterprise system, the analytics engine to report the telemetry data in response to activation or deactivation of the at least one of the one or more features based on the license.

Software defined silicon implementation and management

Examples herein relate to assigning, by a system agent of a central processing unit (CPU), an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent. Avoiding throttling of the system agent can include maintaining a minimum performance level of the system agent. A minimum performance level of the system agent can be based on a minimum operating frequency. Assigning, by a system agent of a central processing unit, an operating frequency to a core group based priority level of the core group while avoiding throttling of the system agent can avoid a thermal limit of the CPU. Avoiding thermal limit of the CPU can include adjusting the operating frequency to the core group to avoid performance indicators of the CPU. A performance indicator can indicate CPU utilization corresponds to Thermal Design Point (TDP).

Platform slicing of central processing unit (CPU) resources

A system includes a processor coupled to an integrated circuit. The processor includes a non-volatile memory to store instructions to perform a boot process. The boot process is discontinued to prevent unauthorized use of the processor if a value received from the integrated circuit in response to a first value sent to the integrated is not valid.

Method and apparatus to prevent unauthorized operation of an integrated circuit in a computer system

An apparatus and method for intelligently scheduling threads across a plurality of logical processors. For example, one embodiment of a processor comprises: a plurality of cores to be allocated to form a first plurality of logical processors (LPs) to execute threads, wherein one or more logical processors (LPs) are to be associated with each core of the plurality of cores; scheduling guide circuitry to: monitor execution characteristics of the first plurality of LPs and the threads; generate a first plurality of LP rankings, each LP ranking including all or a subset of the plurality of LPs in a particular order; and store the first plurality of LP rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of LPs using the first plurality of LP rankings; a power controller to execute power management code to perform power management operations including independently adjusting frequencies and/or voltages of one or more of the plurality of cores; wherein in response to a core configuration command to deactivate a first core of the plurality of cores, the power controller or privileged program code executed on the processor are to update the memory with an indication of deactivation of the first core, wherein responsive to the indication of deactivation of the first core, the scheduler is to modify the scheduling of the threads.

Growing community of inventors

Hillsboro, OR, United States of America

Vasudevan Srinivasan