Broadcom Corporation

Thomson Licensing

Thomson Licensing S.a.

Vasudevan Parthasarathy

Howard A Baumer

Linda Ying

Chung-Jue Chen

Ali Ghiasi

Afshin Momtaz

Abbas Amirichimeh

John Louie

William G Bliss

Vivek Telang

Hong Chen

John S Wang

Rajesh Satapathy

Jay Proano

Jun Cao

Sudeep Bhoja

Kumar Ramaswamy

John Sidney Stewart

Namik Kocaman

Ivonete Markman

Magesh Valliappan

Gavin Derek Parnaby

Jaehyeong Kim

Lorenzo Longo

Michael Furlong

Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.

High speed time-interleaved ADC gain offset and skew mitigation

Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.

Method and apparatus for reference-less repeater with digital control

Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor. Using the microprocessor, the capture memory module calibrates the digital correction module until the output of the digital correction module is within a desired range.

Flexible ADC calibration technique using ADC capture memory

Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided.

Generalized transmit pre-coding for optical and backplane channels

Systems and methods that facilitate on-chip testing are provided. An integrated circuit can include a transmitter configured to transmit a communications signal via a communications channel. The integrated circuit can also include a receiver configured to receive the communications signal via the communications channel. A jitter creation module also can form part of the integrated circuit and can introduce jitter into the system thereby allowing for on-chip jitter testing. The jitter creation module can form either part of the transmitter or receiver and can introduce the jitter by phase interpolation.

On-chip interferers for standards compliant jitter tolerance testing

In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Systems for high-speed backplane applications using pre-coding

According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Multi-protocol communications receiver with shared analog front-end

A transceiver system is disclosed that includes a plurality of transceiver chips. Each transceiver chip includes one or more SERDES cores. Each SERDES core includes one or more SERDES lanes. Each SERDES lane includes a receive channel and a transmit channel. The transmit channel of each SERDES lane is phase-locked with a corresponding receive channel. The transceiver system has the capability of phase-locking a transmit clock signal phase of a transmitting component with a receive clock signal phase of a receiving component that is a part of a different SERDES lane, a different SERDES core, a different substrate, or even a different board. Each SERDES core receives and transmits data to and from external components connected to the SERDES core, such as hard disk drives. A method of transferring data from a first external component coupled to a receive channel to a second external component coupled to a transmit channel is also disclosed.

Method and transceiver system having a transmit clock signal phase that is phase-locked with a receive clock signal phase

Systems for high-speed backplane applications using FEC encoding

Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter ('ADC') block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

Electronic dispersion compensation utilizing interleaved architecture and channel identification for assisting timing recovery

Embodiments include a system for performing electronic dispersion compensation on an information-bearing signal transmitted over a communication channel. The system may include a channel identification module configured to receive a first digitized version of the information bearing signal and an equalized version of the information-bearing signal, and may be configured to determine an impulse response of the communication channel based thereon. The system may include a time varying phase detector configured to receive the equalized version of the information bearing signal, a second digitized version of the information-bearing signal, and the impulse response, and may be further configured to generate a reference wave based on the impulse response and the equalized version of the information-bearing signal. The time varying phase detector may be configured to generate a phase signal based on the reference wave and on an error signal determined from the reference wave and the second digitized version of the information-bearing signal.

Growing community of inventors

Irvine, CA, United States of America

Vasudevan Parthasarathy