Intel Corporation

Arizona State University

Arizona Board of Regents, a Body Corporate

Vasudeva Atluri

Sairam Agraharam

Carlton E Hanna

Dongming He

Sujit Sharan

Debendra Mallik

James D Bradley

Nicole Herbots

Matthew Escobido

Robert Culbertson

Justin Shaw

Banerjee Swati

Jiong Xiang

Quinton B Hurst

The invention provides novel methods for preparing semiconductor substrates for the growth of an ultra-thin epitaxial interfacial phase thereon. The invention additionally provides the ultra-thin epitaxial interfacial phase formed on a semiconductor substrate prepared by the methods of the invention. Epitaxiality of the interfacial phase is ensured by maintaining the cleaned semiconductor substrate in a static and inert atmosphere prior to oxidation to form the interfacial phase. Such interfacial phase are useful as capping layers and dielectric layers for semiconductor devices.

Methods for preparing semiconductor substrates and interfacial oxides thereon

In one embodiment, the invention provides a method comprising fabricating a die bump on a die, the die bump being shaped and dimensioned to at least reduce the flow of solder material used, to attach the die bump to a package substrate, towards an under bump metallurgy (UBM) layer located below the die bump. Advantageously, the method may comprise performing a substrate reflow operation to attach the package substrate to the die bump, without performing a separate wafer reflow operation to reflow the die bump.

C4 joint reliability

Mechanical stresses are reduced between an electronic component having relatively low fracture toughness and a substrate having relatively greater fracture toughness. In an embodiment, the component may be a die having mounting contacts formed of a low yield strength material, such as solder. A package substrate has columnar lands formed of a relatively higher yield strength material, such as copper, having a relatively higher melting point than the component contacts and having a relatively high current-carrying capacity. The component contacts may be hemispherical in shape. The lands may be substantially cylinders, truncated cones or pyramids, inverted truncated cones or pyramids, or other columnar shapes. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Integrated circuit packages with reduced stress on die and associated methods

Integrated circuit packages with reduced stress on die and associated substrates, assemblies, and systems

A semiconductor processing method capable of producing highly ordered, ultra thin dielectrics, including gate oxide and other semiconductor dielectrics, and interphase phases with low defect density. The process includes a degrease step, an etch, primary oxidation and then a passivation step which utilizes hydrofluoric acid to passivate the cleaned silicon surface with hydrogen. Dielectric layers may then be formed with low interface defect density, low flat band voltages and low fixed charge on semiconductor substrates.

Long range ordered semiconductor interface phase and oxides

Growing community of inventors

Scottsdale, AZ, United States of America

Vasudeva Atluri