Intel Corporation

Marvell International Limited

Other

Vasudev Bibikar

Sankaran M Menon

Naveendran Balasingam

P Reddy Sahajananda

Sunghyun Koh

Paul Aerick Lambert

Mark Norman Fullerton

James Robert Feddeler

Minda Zhang

David Joseph Hawkins

Rajith Kumar Mavila

Moorthy Rajesh

Mark N Fullterton

Rajesh Poornachandran

Varghese George

Sanjeev S Jahagirdar

Ankush Varma

Kristoffer Fleming

David W Browning

Robert E Gough

Achmed Rumi Zahir

Michael T Klinglesmith

Darren S Crews

Douglas Raymond Moran

Ajaya V Durg

Guy G Sotomayor

Nancy G Woodbridge

William Knolla

Ashraf H Wadaa

Quang T Le

Anil K Sabbavarapu

Amit Dor

Irwin J Vaz

Arpit Shah

James A Bish

Aswin Ramachandran

Hartej Singh

Patrick Kam-Shing Leung

Ranjani Sridharan

Trevor S Love

Chin Seng Lu

Nabil F Kerkiz

Ryan R Pinto

Described is an apparatus which comprises: a first voltage regulator (VR) having a reference input node; and a first multiplexer to provide a reference voltage to the reference input node and operable to select one of at least two different reference voltages as the reference voltage.

Apparatus and method to debug a voltage regulator

In one embodiment, a processor includes: at least one core to execute a workload; a voltage regulator to provide an operating voltage to the at least one core; and a power controller coupled to the voltage regulator. The power controller may control the voltage regulator to provide the operating voltage, and may have a voltage regulator control circuit to select one of a plurality of power state profiles based at least in part on a classification of the workload, and to cause an update to a power state of the voltage regulator according to the selected power state profile. Other embodiments are described and claimed.

System, apparatus and method for dynamic power state scaling of a voltage regulator for a processor

A computing device, system and method. The computing device includes a memory storing instructions, and a processing circuitry coupled to the memory. The processing circuitry is configured to execute the instructions to process a first control signal and a second control signal from respective first and second control pins of a computing platform. The processing circuitry is further to transition the computing platform, based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, between a low power state and a retention power state without transitioning to an operational power state in between.

Mechanism to enter or exit retention level voltage while a system-on-a-chip is in low power mode

A method and apparatus (e.g., semiconductor device) for setting voltages (e.g., guardbands) using 'in situ,' or on-die, silicon measurements are described. In one embodiment the semiconductor device comprises: a process monitor to measure silicon parameters of the semiconductor device; and a controller coupled to the process monitor to set a voltage for use on at least a portion of the semiconductor device based on silicon process monitor measurements.

Method and apparatus for enhancing guardbands using 'in-situ' silicon measurements

The present disclosure is directed to logging random 'chirps' of IoT devices and rebroadcasting these chirps to other devices on demand. An apparatus consistent with the present disclosure includes a transmitter to communicate with a network of wireless-communication-enabled devices. The apparatus also includes a receiver to detect communications transmitted from the wireless-communication-enabled device. Further, the apparatus includes control unit logic to tally the number of electrical signals emitted from each wireless-communication-enabled device. In addition, the apparatus includes memory to store the number of emitted electrical signals. The apparatus further includes a power unit electrically coupled to the transmitter, receiver, and memory.

Internet of things electronic signal aggregator and repeater

In an embodiment, a processor includes at least one functional block and a central power controller. The at least one functional block may include at least one block component and block power logic. The block power logic may be to: receive a first request to initiate a first reduced power mode in the at least one functional block, and in response to the first request, send a notification signal to a central power controller. The central power controller may be to, in response to the notification signal: store a first state of the at least one functional block, and initiate the first reduced power mode in the at least one functional block. Other embodiments are described and claimed.

System and method for initiating a reduced power mode for one or more functional blocks of a processor based on various types of mode request

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Technologies for low-power standby display refresh

Various embodiments are generally directed to an apparatus, method and other techniques for determining a sleep configuration state for each of a plurality of subsystems having an associated subsystem sleep control register for entry into a lower power state, configuring each of the associated subsystem sleep control registers with the sleep configuration state for each of the subsystems and enabling the sleep configuration state for each of the subsystems in parallel when transitioning to the lower power state.

Techniques for putting platform subsystems into a lower power state in parallel

The present disclosure includes apparatus, systems, digital logic circuitry and techniques relating to data encoding. A method performed by a system on a chip (SOC) includes receiving data to be output to a memory unit external to the SOC. Also a key for scrambling the received data is received. A proper subset of the key is identified and used to scramble the received data. The scrambled data is output to the memory unit external to the SOC.

Securing external memory data

An indication that a power supply is ramped up to a threshold level is received. A circuit is woken up in response to receiving the indication if a control field of configuration information is in a first state, and the circuit is not woken up in response to receiving the indication if the control field of configuration information is in a second state.

Method and apparatus for waking up a circuit

An electronic circuit comprises at least one digital logic circuit; and a power control circuit. The power control circuit is operable to adjust the voltage of a power signal supplied to the at least one digital logic circuit in response to a change in a clock frequency provided to the at least one digital logic circuit. In a further embodiment, the power controller is operable to increase the voltage of the power signal applied to the digital logic circuit before a frequency increase is made, and is operable to decrease the voltage of the power signal applied to the digital logic circuit after a frequency decrease is made.

Frequency-dependent voltage control in digital logic

A processor may receive multiple signals corresponding to potential power faults. A control register in the processor may specify actions to be taken for each of the potential power faults.

Power fault handling method, apparatus, and system

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Austin, TX, United States of America

Vasudev Bibikar