Intel Corporation

Vassoudevane Lebonheur

Debendra Mallik

Rahul N Manepalli

Robert Starkston

Tian-An Chen

Richard J Harries

Terry Lee Sterrett

Eduardo J Bolanos

Gregory J Lemke

Terrence C Caskey

A molding compound cap structure is disclosed. A process of forming the molding compound cap structure is also disclosed. A microelectronic package is also disclosed that uses the molding compound cap structure. A method of assembling a microelectronic package is also disclosed. A computing system is also disclosed that includes the molding compound cap structure. The molding compound cap includes a configuration that exposes a portion of a microelectronic device.

Mold compound cap in a flip chip multi-matrix array package and process of making same

A die attachment includes a placement head, a platen, and a vibration mechanism to vibrate at least a selected one of the placement head and platen while a die and a substrate mounted on the placement head and the platen, respectively, are in contact.

Vibratable die attachment tool

A semiconductor chip package, an electronic system, and a method of manufacturing such package. A lower structure includes a lower insulating layer and a metal layer made of separate electrical conductors. A wall defines a cavity on the metal layer. Electrical conductors extend from the metal layer to contact points elsewhere in the semiconductor chip package. Conductor members are positioned on the electrical conductors of the metal layer. A semiconductor chip is positioned on the conductor members within the cavity, with an isolation area between the semiconductor chip and the wall. The electrical contacts on the semiconductor chip contact the conductor members to couple the semiconductor chip to the contact points. Underfill material is provided within the isolation area between the perimeter surface and the wall, and is prevented by the wall from spreading to other areas. Placement of the semiconductor chip within the cavity reduces the package thickness.

Semiconductor chip package and method of manufacturing same

A method of making a microelectronic assembly is provided. Wetting and flow characteristics of a no-low underfill material are improved by preheating the no-flow underfill material. In one embodiment, the no-flow underfill material is preheated in a dispensing apparatus before being dispensed on a substrate. A die is then placed on the substrate, whereafter interconnection elements between the die and the substrate are reflowed and the no-flow underfill material is cured. In another embodiment, the no-flow underfill material is preheated after a die is placed on a substrate with the no-flow underfill material between the die and the substrate. In a further embodiment, a no-flow underfill material is dispensed on a die, whereafter a substrate is placed on the die with the no-flow underfill material between the substrate and the die.

Method of making a microelectronic assembly

Embodiments of the methods of the present invention provide a Molded Matrix Array Package (MMAP) carrier substrate panel that prevents underfill wetting in the inter-die areas. Surface treatments are provided via plasmas and/or patterned chemical depositions that reduce the surface free energy of the inter-die area to below the surface free energy of the underfill material. The surface treatments prevent the underfill material from wetting the carrier substrate panel and therefore encroachment upon the inter-die area. This provides a underfill material-free inter-die area allowing adhesion between the mold compound and carrier substrate.

Surface treatment for microelectronic device substrate

A microprocessor package and a method of dissipating heat therefrom have improved thermal performance by utilizing low modulus thermal interface material between the flip chip, central processing unit and a heat spreader in the package. A modulus of elasticity of the thermal interface material in the kPa range is preferably provided by a cured, filled polymer gel which is lightly crosslinked. The gel thermal interface material enables the package to have a post end-of-line and post reliability testing thermal resistance across the thermal interface material between the flip chip and the heat spreader of <0.45 cm &deg; C./Watt. Mitigation of thin film cracking in die and prevention of interfacial delamination upon temperature cycling are also attained.

Growing community of inventors

Tempe, AZ, United States of America

Vassoudevane Lebonheur