National Semiconductor Corporation

Vassili M Kitch

Michael E Thomas

Kevin Carl Brown

Joost J Vlassak

First material () is situated on the surface of a substructure (and) and in an opening (), such as a Wench, that extends partway through the substructure. Second material () is situated on the first material in the opening. A physical sputter etch is performed on the structure while it is in a sputter etch module () to remove the parts of the first material overlying the substructure's surface and situated above the opening and to remove part of the second material overlying the first material in the opening so that remaining parts of the first and second materials are situated in the opening. The so-modified structure is transferred from the sputter etch module under a substantial vacuum, normally via a transfer module (), to a deposition module (, or) where a layer of third material is deposited over the substructure's surface and over the parts of the first and second materials in the opening.

Fabrication technique using sputter etch and vacuum transfer

A copper-containing layer suitable for an electrical interconnect in a device such as an integrated circuit is created by a procedure in which a trench () is formed through a dielectric layer () down to a substrate (). A diffusion barrier () is provided over the dielectric layer and into the trench. Copper () is deposited over the diffusion barrier and into the trench. Chemical mechanical polishing is utilized to remove the copper outside the trench down substantially to the diffusion-barrier material overlying the dielectric layer. A sputter etch, typically of the reactive type, is then performed to substantially remove the diffusion-barrier material overlying the dielectric layer. The sputter etch typically removes copper above and/or in the trench at approximately the same rate as the diffusion-barrier material so as to substantially avoid the undesirable dishing phenomenon.

Fabrication of copper-containing region such as electrical interconnect

A bipolar transistor structure that includes a semiconductor material substrate that has a bottom substrate and base region of a first conductivity type and a buried layer, collector region and sink region of a second conductivity type. The substrate has an extrinsic base region of the first conductivity type and an emitter region of the second conductivity type, both of which extend from the substrate's upper surface into the base region. The bipolar transistor structure also includes a single patterned polysilicon layer with a first polysilicon portion of the first conductivity type in contact with the extrinsic base region and a second polysilicon portion of the second conductivity type in contact with the emitter region. The bipolar transistor structure is compact since contact to the extrinsic base region is made by the first polysilicon portion, which can be formed to a minimum dimension and self-aligned to the extrinsic base region. The extrinsic base and base regions can, therefore, be small, providing a low extrinsic base resistance, low base resistance and low collector-base capacitance. A process for forming such a bipolar transistor structure includes depositing a polysilicon layer and then implanting dopant ions of the first and second conductivity types into the polysilicon layer using first and second patterned mask layers, respectively. After etching the polysilicon layer, a thermal treatment creates an extrinsic base region and an emitter region by diffusing ions from the etched polysilicon layer. The process is inexpensive since it employs only a single patterned polysilicon layer.

Method for manufacturing a compact bipolar transistor structure

In accordance with one embodiment of the invention, a diffusion barrier layer is formed in a copper interconnect structure by first forming a layer of intermetal dielectric material on an underlying layer of conductive material. A pattern of dual damascene structures is then formed in the interconnect dielectric layer. An adhesion layer is then formed on exposed sidewalls of the damascene structure and on the upper surface of the intermetal dielectric material. The adhesion-layer-lined dual damascene structures are then filled with a conductive material that includes copper. The copper-including conductive material is then planarized to the upper surface of the intermetal dielectric material. Intermetal dielectric material is then removed to expose the conductive material. A diffusion barrier material is then deposited on exposed surfaces of the conductive material. Low k dielectric material is then disposed over the entire interconnect structure to fill the gaps, thus providing a low k solution and structural integrity to the interconnect.

Structure and method for controlling copper diffusion and for utilizing low K materials for copper interconnects in integrated circuit structures

Compact bipolar transistor structure

A technique is provided for laying out vias between metal layers in an integrated circuit structure utilizing conventional Metal n and Metal N&plus;1 databases. A first database (Metal n) is created that defines a lower conductive layer. A second database (Metal N&plus;1) is created that defines an upper conductive layer. Selected intersections of the first database and the second database are then determined, thereby creating a third database (via n) that defines a pattern of vias between the lower conductive layer and the upper conductive layer. This allows interconnect vias to be optimized in size and shape, thus providing lowest possible interlayer resistance, which in turn provides the best possible circuit performance and reliability.

Method op optimizing vias between conductive layers in an integrated circuit structure

A vertically-isolated bipolar transistor occupying reduced surface area is fabricated by circumscribing an expected active device region within a first narrow trench. The first trench is filled with sacrificial material impermeable to diffusion of conductivity-altering dopant, and then isolation dopant of a conductivity type opposite to that of the substrate is introduced into the trench-circumscribed silicon region. The introduced isolation dopant is then thermally driven into the substrate, with lateral diffusion of isolation dopant physically constrained by the existing first narrow trench. Epitaxial silicon is then formed over the substrate, with polysilicon formed in regions overlying the filled narrow trench. A second, wider trench encompassing the first trench is etched to consume epitaxial silicon, polysilicon, and the sacrificial material. The second trench is then filled with dielectric material. Base and emitter structures are formed in the conventional manner within the trench-circumscribed silicon. Constraint of lateral diffusion of isolation-type dopant by the first trench reduces lateral dimensions of the isolation region and of the overall device. The smaller device area permits enhanced device packing density and reduces parasitic capacitance arising between the isolation region and the substrate.

Process for formation of vertically isolated bipolar transistor device

A method for removing a resistive film formed on an electrode to increase the conductive contact area of the electrode positioned in a misaligned contact hole. The method comprises providing a substrate supporting an electrode layer. The electrode layer is etched to produce metal lines. During the processing of the metal lines, a resistive film is formed thereon. The resistive film is removed and a protective barrier is formed on the metal lines. A dielectric layer is formed on the substrate, including the metal lines. The dielectric layer is subsequently patterned to form contact holes or vias to expose a portion of the metal lines. The contact holes are filled with plugs such that a second electrode layer can be formed on the dielectric layer and the plugs.

Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects

A method for determining the temperature of a wafer during processing is disclosed. A test wafer is specially prepared in conjunction with a calibration chart. The difference in stack sheet resistance of the test wafer before and after processing is plotted onto the calibration chart to determine the temperature of the test wafer during processing.

Method of wafer temperature measurement

Structure and method for controlling copper diffusion and for utilizing

A copper interconnect structure is formed in a semiconductor device using self-aligned copper or tungsten via pillars to connect upper and lower copper interconnect layers separated by a dielectric. The lower copper interconnect layer is formed on an underlying layer. The via pillars are formed on the lower copper interconnect layer. The copper upper interconnect layer is formed to make electrical contact to exposed upper surfaces of the via pillars.

Self-aligned copper interconnect structure and method of manufacturing

A process for forming a via in a semiconductor device using a self-aligned tungsten pillar to connect upper and lower conductive layers separated by a dielectric. A Ti/TiN layer is formed on an underlying substrate layer, an aluminum-copper layer is formed on the Ti/TiN layer, a TiN layer is formed on the aluminum-copper layer and a tungsten layer is formed on the TiN layer. In one continuous etching step, the stack of tungsten, TiN, Al--Cu, Ti/TiN is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the substrate layer and the conductive stack. The wafer is then planarized to expose the top of the tungsten layer. The wafer is again patterned and the tungsten is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the tungsten pillar. An aluminum-copper layer is then formed on the overlying dielectric to make electrical contact to the exposed surface of the tungsten pillar. Since the etch of the upper aluminum-copper layer to form the upper interconnect pattern is highly selective to tungsten, the tungsten is not etched if there is misalignment of the upper metal mask.

Self-aligned interconnect using high selectivity metal pillars and a via

A process for forming a via in a semiconductor device using a self-aligned metal pillar to connect metal layers separated by a dielectric. A first aluminum layer is formed on an oxide layer overlying a semiconductor substrate, a titanium nitride layer is formed on the aluminum layer and finally a second aluminum layer is formed on the titanium nitride layer. In one continuous etching step, the stack of aluminum/titanium nitride/aluminum is then patterned and etched. A first dielectric is deposited overlying the exposed regions of the oxide layer and the formed metal stack. The wafer is then planarized exposing the top of the second aluminum layer. The wafer is again patterned and the second layer of aluminum is etched using the titanium nitride as an etch stop. A second dielectric is deposited to fill the resulting gaps and CMP processes are used to planarize the wafer and expose the top of the aluminum pillar. A third aluminum layer is formed on the overlying dielectric to make electrical contact to the exposed surface of the pillar.

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San Ramon, CA, United States of America

Vassili M Kitch