Imec Vzw

Interuniversitair Microelektronica Centrum (imec)

Nxp B.v.

Imec

Interuniversitair Micorelektronica Centrum (imec, Vzw)

Vasile Paraschiv

Eric Beyne

Denis Shamiryan

Marc Demand

Boon Teik Chan

Zheng Tao

Anabela Veloso

Efrain Altamirano Sanchez

Kaidong Xu

Eddy Kunnen

Romain Delhougne

Judit G Lisoni

Khashayar Babaei Gavan

Guglielma Vecchio

Martine Claes

The disclosed technology generally relates to semiconductor fabrication, and more particularly to a method of forming a target layer surrounding a vertical nanostructure. In one aspect, a method includes providing a substrate having a substrate surface. The method additionally includes forming a vertical nanostructure extending outwardly from a substrate surface. The vertical nanostructure has a sidewall surface, where the sidewall surface has an upper portion and a lower portion. The method additionally includes forming a target layer at least along the sidewall surface of the vertical nanostructure and on the substrate surface. The method additionally includes forming a protection layer covering the target layer and removing an upper portion of the protection layer, thereby exposing the target layer along the upper portion of the sidewall surface of the vertical nanostructure. Thereafter, the exposed target layer is removed along the upper portion of the sidewall surface of the vertical nanostructure selective towards the protection layer. Thereafter, the remaining protection layer is removed.

Method of forming target layer surrounding vertical nanostructure

A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

Method for producing a pillar structure in a semiconductor layer

A method for removing oxide selective to a material comprising at least silicon and at least nitrogen is disclosed, the method comprising providing in a reactor a structure having a surface comprising a region, wherein said region comprises a material comprising at least silicon and at least nitrogen, providing on said structure an oxide layer overlying at least a part of said region, and removing said oxide layer selective to said material by etching, thereby exposing at least a part of said at least overlaid part of said region, wherein said etching is done only by providing an etchant gas comprising boron, whereby a voltage bias lower than 30 V is applied to the structure.

Method for selective oxide removal

A method of producing a multilayer structure is provided, wherein the method comprises forming a phase change material layer onto a substrate, forming a protective layer, forming a further layer on the protective layer, patterning the further layer in an first patterning step, patterning the protective layer and the phase change material layer by a second patterning step. In particular, the first patterning step may be an etching step using chemical etchants. Moreover, electrodes may be formed on the substrate before the phase change material layer is formed, e.g. the electrodes may be formed on one level, e.g. may form a planar structure and may not form a vertically structure.

Multilayer structure comprising a phase change material layer and method of producing the same

A method for the selective removal of a high-k layer such as HfOover silicon or silicon dioxide is provided. More specifically, a method for etching high-k selectively over silicon and silicon dioxide and a plasma composition for performing the selective etch process is provided. Using a BClplasma with well defined concentrations of nitrogen makes it possible to etch high-k with at a reasonable etch rate while silicon and silicon dioxide have an etch rate of almost zero. The BClcomprising plasmas have preferred additions of 10 up to 13% nitrogen. Adding a well defined concentration of nitrogen to the BCl/Nplasma gives the unexpected deposition of a Boron-Nitrogen (BxNy) comprising film onto the silicon and silicon dioxide which is not deposited onto the high-k material. Due to the deposition of the Boron-Nitrogen (BxNy) comprising film, the etch rate of silicon and silicon dioxide is dropped down to zero. The Boron-Nitrogen (BxNy) comprising film can be removed during the etching process using the right substrate bias (leading to ion bombardment) or after the etching process by a simple water rinse since the Boron-Nitrogen (BxNy) comprising film is water soluble.

Plasma composition for selective high-k etch

A method is disclosed for the selective removal of rare earth based high-k materials such as rare earth scandate high-k materials (e.g. DyScO) over silicon or silicon dioxide. As an example Dy and Sc comprising high-k materials are used as a high-k material in gate stacks of a semiconductor device. The selective removal and etch of this high-k material is very difficult since Dy and Sc (and their oxides) are difficult to etch. The etching could however be easily stopped on them. For patterning of the metal gates comprising TiN and TaN on top of rare earth based high-k layer a chlorine-containing gases (Cland BCl) can be used since titanium ant tantalum chlorides are volatile and reasonable selectivity to other material present on the wafer (Si, SiO) can be obtained. The Dy and Sc chlorides are not volatile, but they are water soluble. This behavior makes it possible that the surface layer of Dy and Sc comprising high-k materials gets chlorinated (brominated) during exposure to the Cl or Br comprising plasma and can be removed after etch by a water rinse.

Selective removal of rare earth based high-k materials in a semiconductor device

A method is provided for the patterning of a stack comprising elements that do not form volatile compounds during conventional reactive ion etching. More specifically the element(s) are Lanthanide elements such as Ytterbium (Yb) and the patterning preferably relates to the dry etching of silicon and/or germanium comprising structures (e.g. gates) doped with a Lanthanide e.g. Ytterbium (Yb doped gates). In case the silicon and/or germanium comprising structure is a gate electrode the silicon and/or germanium is doped with a Lanthanide (e.g. Yb) for modeling the work function of a gate electrode.

Patterning of doped poly-silicon gates

The present invention relates to a method for selectively removing a high-k material comprising providing a high-k material on a semiconductor substrate, and contacting the high-k material with a solution comprising HF, an organic compound, and an inorganic acid.

Growing community of inventors

Kessel-lo, Belgium

Vasile Paraschiv