Other

Renesas Technology Corp.

Vasile Mosneaga

Tetsuya Matsumura

Hiroshi Segawa

Satoshi Kumaki

Atsuo Hanami

When the CPU writes data into a memory, a 0 detection circuit detects the number of bits having the value 0 from the data. When the number of bits with 0 is equal to or larger than the number of bits with 1, the data output from the CPU is provided to the memory under control of a selector. When the number of bits with 0 is fewer than the number of bits with 1, the data output from the CPU is inverted and provided to the memory under control of the selector. Accordingly, the rewriting frequency of each memory cell from 0 to 1 or from 1 to 0 in the memory can be reduced in average. Thus the power consumption of the memory in a data writing mode can be reduced.

Growing community of inventors

Fukuoka-shi, Fukuoka, Japan

Vasile Mosneaga