Cambridge Semiconductor Limited

Cambridge Microelectronics Ltd.

Vasantha Pathirana

Tanya Trajkovic

Florin Udrea

Nishad Udugampola

Gehan Anil Joseph Amaratunga

The invention generally relates to a lateral power semiconductor transistor for example in integrated circuits. In particular the invention relates to Lateral Insulated Gate Bipolar Transistors or other lateral bipolar devices such as PIN diodes. The invention also generally relates to a method of increasing switching speed of a lateral bipolar power semiconductor transistor. There is provided a lateral bipolar power semiconductor transistor comprising a first floating semiconductor region of the first conductivity type located laterally spaced to an anode/drain region and a second floating semiconductor region of the second conductivity type located laterally adjacent the first floating semiconductor region, and a floating electrode placed above and in direct contact to the first and second floating semiconductor regions.

Lateral power semiconductor transistors

We describe a RESURF semiconductor device having an n-drift region with a p-top layer and in which a MOS (Metal Oxide Semiconductor) channel of the device is formed within the p-top layer.

Power semiconductor devices and fabrication methods

This invention generally relates to lateral insulated gate bipolar transistors (LIGBTs), for example in integrated circuits, methods of increasing switching speed of an LIGBT, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT, and methods of fabricating an LIGBT. In particular, a method of suppressing parasitic thyristor latch-up in a bulk silicon LIGBT comprises selecting a current gain &#x3b1;v for a vertical transistor of a parasitic thyristor of the LIGBT such that in at least one predetermined mode of operation of the LIGBT &#x3b1;v&#x3c;1&#x2212;&#x3b1;p where &#x3b1;p is a current gain of a parasitic bipolar transistor having a base-emitter junction formed by a Schottky contact between the a semiconductor surface and a metal enriched epoxy die attach.

Lateral insulated gate bipolar transistors (LIGBTS)

This invention generally relates to LIGBTs, ICs comprising an LIGBT and methods of forming an LIGBT, and more particularly to an LIGBT comprising a substrate region of first conductivity type and peak dopant concentration less than about 1&#xd7;10/cm; a lateral drift region of a second, opposite conductivity type adjacent the substrate region and electrically coupled to said substrate region; a charge injection region of the first conductivity type to inject charge toward said lateral drift region; a gate to control flow of said charge in said lateral drift region; metal enriched adhesive below said substrate region; and an intermediate layer below said substrate region to substantially suppress charge injection into said substrate region from said metal enriched adhesive.

Lateral insulated gate bipolar transistor (LIGBT)

In a power semiconductor device and a method of forming a power semiconductor device, a thin layer of semiconductor substrate is left below the drift region of a semiconductor device. A power semiconductor device has an active region that includes the drift region and has top and bottom surfaces formed in a layer provided on a semiconductor substrate. A portion of the semiconductor substrate below the active region is removed to leave a thin layer of semiconductor substrate below the drift region. Electrical terminals are provided directly or indirectly to the top surface of the active region to allow a voltage to be applied laterally across the drift region.

Semiconductor device and method of forming a semiconductor device

A power semiconductor device has a top surface and an opposed bottom surface below a part of which is a thick portion of semiconductor substrate. At least a portion of a drift region of the device has either no or only a thin portion of semiconductor substrate positioned thereunder. The top surface has a high voltage terminal and a low voltage terminal connected thereto to allow a voltage to be applied laterally across the drift region. At least two MOS (metal-oxide-semiconductor) gates are provided on the top surface. The device has at least one relatively highly doped region at its top surface extending between and in contact with said first and second MOS gates. The device has improved protection against triggering of parasitic transistors or latch-up without the on-state voltage drop or switching speed being compromised.

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Cambridge, United Kingdom

Vasantha Pathirana