Qualcomm Incorporated

Vasantha Kumar Bandur Puttappa

Kunal Mukesh Desai

Umesh Madhusudan Rao

Madhukar Reddy N

Saurabh Sethi

Amulya Srinivasan Margasahayam

Aspects of the present disclosure are directed to techniques and procedures for reducing memory (e.g., DRAM) access latency (e.g., read latency, write latency) due to memory refreshes. In some aspects, a memory refresh scheduling algorithm can take into account of memory access batching (e.g., read batch, write batch). In some aspects, a refresh scheduling algorithm can schedule more or prioritize refreshes to occur during a write batch to reduce memory read access latency because fewer refreshes are scheduled during memory read access. The techniques can be adapted to reduce write latency.

Batching aware techniques for refreshing memory devices

Methods and systems for dynamically controlling buffer size in a computing device in a computing device ('PCD') are disclosed. A monitor module determines a first use case for defining a first activity level for a plurality of components of the PCD. Based on the first use case, a plurality of buffers are set to a first buffer size. Each of the buffers is associated with one of the plurality of components, and the first buffer size for each buffer is based on the first activity level of the associated component. A second use case for the PCD, different from the first use case, is determined. The second use case defines a second activity level for the plurality of components. At least one of the buffers is set to a second buffer size different from the first buffer size based on the second use case.

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Bengaluru, India

Vasantha Kumar Bandur Puttappa