Intel Corporation

Vasanth Ranganathan

Joydeep Ray

Abhishek R Appu

Altug Koker

Prasoonkumar Surti

Balaji Vembu

Kamal Sinha

Sanjeev S Jahagirdar

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Lakshminarayanan Striramassarma

Nicolas C Galoppo Von Borries

Varghese George

Aravindh V Anantaraman

Mike MacPherson

Valentin Andrei

Scott R Janus

James A Valerio

Pattabhiraman K

Eriko Nurvitadhi

Linda L Hurd

Kiran Chand Veernapu

Arthur Hunter, Jr

Anbang Yao

Xiaoming Chen

Brent E Insko

Tatiana Shpeisman

Ping Tak Tang

Michael S Strickland

Rajkishore Barik

Dukhwan Kim

Tsung-Han Lin

Sungye Kim

Nikos Kaburlasos

Ben J Ashbaugh

John Charles Weast

Karol A Szerszen

Travis T Schluessler

Ankur N Shah

David M Puffer

Narayan Srinivasa

Feng Chen

Nadathur Rajagopalan Satish

Mike B Macpherson

Farshad Akhbari

Murali Ramadoss

Sanu K Mathew

Mark A Anders

Himanshu Kaul

Vikranth Vemulapalli

Saurabh Sharma

Adam T Lake

Niranjan L Cooray

Liwei Ma

Guei-Yuan Lueh

Justin E Gottschlich

Lidong Xu

Sara S Baghsorkhi

Atsuo Kuwahara

James M Holland

Chandrasekaran Sakthivel

Karthik Vaidyanathan

Jeffery S Boles

Wenyin Fu

Bhushan M Borole

Xinmin Tian

Eric J Hoekstra

Michael J Norris

Josh B Mastronarde

Jonathan Kennedy

Ashutosh Garg

Jonathan D Pearce

Jill MacDonald Boyce

Carsten Benthin

John H Feit

Tomer Bar-On

Hugues Labbe

Jacek Kwiatkowski

Hema Chand Nalluri

Wei-Yu Chen

Aditya Navale

Narayan Biswal

Deepak Shashidhar Vembar

Stanley J Baran

Abhishek Venkatesh

Gokcen Cilingir

Nilesh V Shah

David J Cowperthwaite

Barnan Das

Robert L Farrell

Sameer Kp

Archie Sharma

Mayuresh M Varerkar

Christopher J Hughes

Michael Apodaca

Eric C Samson

Changliang Wang

Selvakumar Panneer

Fangwen Fu

Pratik M Marolia

Described herein is a partitionable graphics processor having multiple render front ends. The partitions of the graphics processor maintain render functionality when partitioned and enable fault isolation and independent multi-client rendering.

Multi-render partitioning

Embodiments described herein are generally directed to improvements relating to power, latency, bandwidth and/or performance issues relating to GPU processing/caching. According to one embodiment, a system includes a producer intellectual property (IP) (e.g., a media IP), a compute core (e.g., a GPU or an AI-specific core of the GPU), a streaming buffer logically interposed between the producer IP and the compute core. The producer IP is operable to consume data from memory and output results to the streaming buffer. The compute core is operable to perform AI inference processing based on data consumed from the streaming buffer and output AI inference processing results to the memory.

Graphics processing unit processing and caching improvements

A mechanism is described for detecting, at training time, information related to one or more tasks to be performed by the one or more processors according to a training dataset for a neural network, analyzing the information to determine one or more portions of hardware of a processor of the one or more processors that is configurable to support the one or more tasks, configuring the hardware to pre-select the one or more portions to perform the one or more tasks, while other portions of the hardware remain available for other tasks, and monitoring utilization of the hardware via a hardware unit of the graphics processor and, via a scheduler of the graphics processor, adjusting allocation of the one or more tasks to the one or more portions of the hardware based on the utilization.

Coordination and increased utilization of graphics processors during inference

Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

Dynamic memory reconfiguration

Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

Systolic arithmetic on sparse data

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

An apparatus to facilitate efficient data sharing for graphics data processing operations is disclosed. The apparatus includes a processing resource to generate a stream of instructions, an L1 cache communicably coupled to the processing resource and comprising an on-page detector circuit to determine that a set of memory requests in the stream of instructions access a same memory page; and set a marker in a first request of the set of memory requests; and arbitration circuitry communicably coupled to the L1 cache, the arbitration circuitry to route the set of memory requests to memory comprising the memory page and to, in response to receiving the first request with the marker set, remain with the processing resource to process the set of memory requests.

Efficient data sharing for graphics data processing operations

Systems and methods for supporting generic pointers in hardware of a graphics processing unit (GPU) are provided. In various examples, a GPU includes multiple sub-cores each having a processing resource and a load/store pipeline. The processing resource is operable to receive a memory access message including a pointer and a memory type identifier indicative of the pointer representing a generic pointer. The processing resource is further operable to output a load or store operation to the load/store pipeline based on the memory access message, including computing an address for the load or store operation by adding a base address of a named memory type of a plurality of named memory types referenced by the generic pointer to an offset into a memory of the named memory type. The load/store pipeline is operable to, responsive to receipt of the load or store operation, access the memory at the address.

Providing native support for generic pointers in a graphics processing unit

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

Methods and apparatus relating to data initialization techniques. In an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. Other embodiments are also disclosed and claimed.

Data initialization techniques

Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.

Generation and storage of compressed Z-planes in graphics processing

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

One embodiment provides for a graphics processing unit to accelerate machine-learning operations, the graphics processing unit comprising a multiprocessor having a single instruction, multiple thread (SIMT) architecture, the multiprocessor to execute at least one single instruction; and a first compute unit included within the multiprocessor, the at least one single instruction to cause the first compute unit to perform a two-dimensional matrix multiply and accumulate operation, wherein to perform the two-dimensional matrix multiply and accumulate operation includes to compute an intermediate product of 16-bit operands and to compute a 32-bit sum based on the intermediate product.

Instructions and logic to perform floating point and integer operations for machine learning

A mechanism is described for facilitating intelligent thread scheduling at autonomous machines. A method of embodiments, as described herein, includes detecting dependency information relating to a plurality of threads corresponding to a plurality of workloads associated with tasks relating to a processor including a graphics processor. The method may further include generating a tree of thread groups based on the dependency information, where each thread group includes multiple threads, and scheduling one or more of the thread groups associated a similar dependency to avoid dependency conflicts.

Efficient thread group scheduling

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Growing community of inventors

El Dorado Hills, CA, United States of America

Vasanth Ranganathan