Xilinx, Inc.

Vasanth Asokan

Ralph D Wittig

Jorge Ernesto Carrillo

Chukwuweta Chukwudebe

Navaneethan Sundaramoorthy

Sivakumar Velusamy

Raj Kumar Nagarajan

In one embodiment of the present invention, a method is provided for maintaining and storing revision history of a design. The method includes, in response to a first control input by a user, determining, by a processor, module definition parameters that have changed from a design file. The changed module definition parameters are stored in the design file. For each changed module definition parameter, revision data are appended to revision history data. The revision data indicates a revision identifier, a module definition parameter identifier, and an updated value of the changed module definition parameter.

Revision history storage and maintenance

A novel coprocessor interface providing memory access without traversing the main processor, and methods of operating the same. A system includes a bus, a processor circuit, a memory circuit, a multi-channel memory controller, and at least one coprocessor. The processor circuit is coupled to the bus, the multi-channel memory controller is coupled between the bus and the memory circuit, and the coprocessors are coupled to both the processor circuit and the multi-channel memory controller. This circuit arrangement provides dedicated high speed channels for data access between the coprocessors and the memory circuit, without traversing the processor circuit or the bus. Thus, non-standard (e.g., non-sequential) data transfer protocols can be supported. In some embodiments, the system is implemented in a programmable logic device (PLD). The processor circuit can be, for example, a microprocessor included as hard-coded logic in the PLD, or can be implemented using programmable logic elements of the PLD.

Coprocessor interface architecture and methods of operating the same

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San Jose, CA, United States of America

Vasanth Asokan