Cadence Design Systems, Inc.

Vasant Ramabadran

Ophir Turbovich

Akash Sharma

Chun-Kuen Ho

A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided.

Support for multiple user defined assertion checkers in a multi-FPGA prototyping system

A method for on-the-fly determination of leakage power and temperature of an electronic circuit design is provided. The method includes calculating a dynamic power of the electronic circuit design. The method also includes calculating a total power consumption of the electronic circuit design. The method further includes averaging the total power consumption to obtain an average total power, determining a temperature of the electronic circuit design based on the average total power, and determining a leakage power of the electronic circuit design based on the temperature. A system and a non-transitory, computer-readable medium storing computer-readable instructions to perform the above method are also provided.

Systems and methods for on-the-fly temperature and leakage power estimation in electronic circuit designs

An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.

Implementing synchronous triggers for waveform capture in an FPGA prototyping system

An apparatus and method for fast phase aligned local generation of design clocks on a multiple FPGA system via clock generator replication is described. The apparatus includes a reference clock that generates a clock signal have a reference frequency and a plurality of programmable logic devices. Each programmable logic device includes phase locked loop circuitry that receives the clock signal from the reference clock and generates a local reference clock signal having a frequency based on the reference frequency and a clock generator that receives the local reference clock signal and generates local design clocks based on the local reference clock signal. Because each local design clock generator is synchronized by the same reference clock over a low skew line, the edges of the local design clocks are aligned.

System and method of fast phase aligned local generation of clocks on multiple FPGA system

An apparatus and method is described for low skew phase generation for multiplexing signals using limited global low skew lines on a multiple FPGA system. The apparatus includes a reference clock programmed to generate a clock signal and programmable logic devices. The programmable logic devices include I/O terminals, combinational logic coupled to the I/O terminals, programmable logic coupled to the combinational logic, a phase generator programmed to receive the clock signal from the reference clock and to generate a phase clock based on the clock signal and a plurality of phase enable signals based on the phase clock, low skew lines to distribute the phase enables with minimal skew caused by routing delays, and flip-flops programmed to have a clock input driven by the phase clock, a data input coupled to ground, and a data output coupled to the combinational logic. Furthermore, synchronous preset inputs of the flip-flops receive the low skew phase enable signals to control transmission design signals by one of the I/O terminal.

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San Jose, CA, United States of America

Vasant Ramabadran