Nxp Usa, Inc.

Varun Sethi

Prabhjot Singh

Wasim Khan

Deepak Kumar

Udit Kumar

A method to retrieve transaction address resulting in PCIe completion timeout includes monitoring a Peripheral Component Interconnect Express (PCIe) controller to detect a Completion Timeout (CTO) transmitted therefrom. A Master Identification (ID) of a Master and a transaction address of a transaction are stored in a configuration space, in response to detecting the CTO, wherein the transaction originates from the Master and the CTO is signaled in response to the transaction. The CTO is responded to with the Master identified by the Master ID in the configuration space.

Method to retrieve transaction address resulting in an uncorrectable PCIe error

A method, system, apparatus, and architecture are provided for detecting failure of a PCIe endpoint device by scanning an extended configuration space for each connected PCIe endpoint device to detect a first PCIe endpoint device that supports advance status reporting, and then by programming a first predetermined value and a second predetermined value, respectively, into an endpoint response register and a root complex request register of a dedicated memory control word in the extended configuration space for the first PCIe endpoint device, where the second predetermined value signals a request to the first PCIe endpoint device to update the endpoint response register of the dedicated memory control word with a new status value so that, after a minimum specified delay, a report that the first PCIe endpoint device has failed may be generated in response to detecting that the first predetermined value is stored in the endpoint response register.

Growing community of inventors

Noida, India

Varun Sethi