International Business Machines Corporation

Globalfoundries Inc.

Varun Mallikarjunan

Satish Kumar Sadasivam

Prathiba Kumar

Sangram Alapati

Manoj Dusanapudi

Rajan Ravindran

Jayakumar N Sankarannair

Sairam Kamaraju

Subrat K Panda

Bhavesh Dhanji Budhabhatti

Kumar Prathiba

Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions. (124 words)

Verification of dynamic logical partitioning

Using an 'optimized' test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.

Detecting missing write to cache/memory operations

Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.

A mechanism is provided for context-aware irritation of a micro-processor. At each executed phase in a set of phases of a test case being executed on a set of micro-processors, a determination is made of a set of characteristics associated with the given executed phase of the test case. Based on the set of determined set of characteristics associated with the given executed phase, a determination is made of an irritation to be executed alongside the given executed phase of the test case. The determined irritation is then executed alongside the given executed phase of the test case.

Tightly-coupled context-aware irritator thread creation for verification of microprocessors

A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least one action is performed on each controlled node mapped to the controlling node. After performing the at least one action on each controlled node mapped to the controlling node or responsive to the node failing to be a controlling node, a self-modifying branch test pattern is executed based on the selected execution pattern in the condition register through the set of nodes. Responsive to the self-modifying branch test pattern ending, values output from the execution unit during execution of the self-modifying branch test pattern are compared to a set of expected results. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Validating cache coherency protocol within a processor

A method for dynamic optimization of thread assignments for application workloads in an simultaneous multi-threading (SMT) computing environment includes monitoring and periodically recording an operational status of different processor cores each supporting a number of threads of the thread pool of the SMT computing environment and also operational characteristics of different workloads of a computing application executing in the SMT computing environment. The method further can include identifying by way of the recorded operational characteristics a particular one of the workloads demonstrating a threshold level of activity. Finally, the method can include matching a recorded operational characteristic of the particular one of the workloads to a recorded status of a processor core best able amongst the different processor cores to host execution in one or more threads of the particular one of the workloads and directing the matched processor core to host execution of the particular one of the workloads.

Dynamic optimization of thread assignments for application workloads in parallel computing

A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An execution pattern is selected from a set of execution patterns thereby forming a selected execution pattern. The selected execution pattern is loaded into a condition register. The branch test pattern is executed by an execution unit based on the selected execution pattern in the condition register. Responsive to the branch test pattern ending, values output from the execution unit during execution of the branch test pattern are compared to a set of expected results. Responsive to a match of the comparison, the process is repeated for each execution pattern in the set of execution patterns. Responsive to a match of the comparison for the execution patterns in the set of execution patterns, the execution unit is validated.

Effective validation of execution units within a processor

A post-silicon testing apparatus, method, and computer program product provide for runtime coverage measurement methodology to measure the architectural events in hardware. Measurement of all architectural events discernable from the instructions and architectural state changes are tracked and recorded. A mechanism to ensure capturing of maskable events is also provided. A feedback driven test-generation approach is enabled by the runtime coverage measurement. The runtime coverage measurement system presents a live view of the comprehensive architectural event coverage to the user/tester. The methodology can be implemented on an operating system environment and also as a standalone/bare-metal tool.

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Bengaluru, India

Varun Mallikarjunan