Intel Corporation

Varsha Regulapati

Aliasgar S Madraswala

Naga Kiranmayee Upadhyayula

Xin Guo

Yogesh B Wakchaure

David J Pelster

Purval Shyam Sule

Donia Sebastian

Neelesh Vemula

Curtis A Gittens

Sriram Balasubrahmanyam

Heonwook Kim

Jong Tai Park

Manjiri M Katmore

Independent multi-plane commands for non-volatile memory devices are described. In one example, a three-dimensional (3D) NAND memory device includes 3D NAND dies, each die including multiple planes of memory cells. The device includes input/output (I/O) circuitry to receive multiple commands from a host, each of the received commands to access one of the planes. The device includes logic (which can be implemented with, for example, an ASIC controller, firmware, or both) to queue the commands in separate queues for each of the planes based on a target plane of each of the commands. The logic issues the commands to their target planes independent of other planes' status, and tracks completion status of the commands independently for each plane.

Independent NAND memory operations by plane

In connection with data pin timing calibration with a strobe signal, examples provide for determination of pass/fail status of a pin from multiple pass/fail results in a single operation. Determination of pass/fail results for multiple pins based on multiple applied trim offsets can be made in parallel. Accordingly, a time to determine pass/fail results from multiple trim values for a pin can be reduced, which can enable faster power-up of NAND flash devices.

Techniques for providing signal calibration data

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Folsom, CA, United States of America

Varsha Regulapati