National Semiconductor Corporation

Juniper Networks, Inc.

Varkey Paul Alapat

Sharada Yeluri

Shahriar Ilislamloo

Raymond Scott Chan

Shunn-Cheng Jang

Emdadur R Khan

A system receives data in multiple streams from an upstream device. The system temporarily stores the data in a first buffer and asserts a forward flow control signal when a capacity of the first buffer exceeds a first threshold value. The system reads the data from the first buffer and selectively processes the data based on the forward flow control signal. The system temporarily stores the selectively processed data in a number of second buffers, generates a backward flow control signal when a capacity of one of the second buffers exceeds a second threshold value, and sends the backward flow control signal to the upstream device.

Flow control for multi-level buffering schemes

Flow control systems and methods for multi-level buffering schemes

A servomechanism controller for controlling the movement and positioning of a servomechanism (such as that of an actuator assembly for the read/write heads of a hard disk drive assembly) in accordance with an improved 'bang-bang' seek technique includes at least one neural network. In one embodiment, a single neural network, connected to a plant with servomechanism, receives two input positioning signals and provides an output positioning signal. One input positioning signal represents a desired servomechanism position, while the other represents its present position. The output positioning signal represents a positioning time period within which the servomechanism will reach the desired position plus a deceleration time period within the positioning time period upon the termination of which the servomechanism will reach its desired position. In another embodiment, one neural network, connected to the plant, receives an input positioning signal and provides an output positioning signal and a status signal. The input positioning signal represents a desired servomechanism position. The output positioning signal represents a positioning time period within which the servomechanism will reach its desired position. The status signal represents a control status of the neural network. Another neural network, also connected to the plant, receives the status signal plus a feedback signal and provides a correction signal. The feedback signal represents the present servomechanism position, while the correction signal represents a deceleration time period within the positioning time period upon the termination of which the servomechanism reaches its desired position.

Intelligent servomechanism controller

A configurable integrated circuit includes a first register having N EPROM cells, and a second register having N EPROM cells, each EPROM cell in the second register corresponding to a distinct one of the N EPROM cells in the first register. Register programming circuits store a set of N binary configuration values in the first register and store boolean complements of the N binary configuration values in the second register. N configuration value sensing circuits are used to read the EPROM cells and generate N configuration signals. Each configuration value sensing circuit is a set/reset latch coupled to one EPROM cell in the first register and the corresponding EPROM cell in the second register. Under normal operating conditions, the latch generates a configuration signal corresponding to the configuration value stored in the one EPROM cell in the first register. A strengthening circuit protects the sensing circuit from alpha particle radiation by applying a strengthening current to each latch after the latch has already reached a stable state. The configurable integrated circuit has a multiplicity of configurable circuits, each configurable circuit having at least one transistor that receives at least one of the N configuration signals and configures the configurable circuit in accordance therewith.

Configurable integrated circuit having true and shadow EPROM registers

A memory array such as an EPROM device includes circuitry that permits testing of a I/O portion of the device without writing data to the EPROM. A data program block that applies a data dependent high voltage pulse to a selected column line for programming can be set to programming or test mode. In the normal, or programming mode, the data input to the data program block is output to the EPROM memory array as is normally required to write to the device. In the test mode, the data output from the data program block controllably connects or decouples the array input line to ground depending upon a binary state of the the input signal. A test output is evaluated using the same sense amp used to evaluate data read from a memory cells of the EPROM array during normal read operations. To prevent writing to the memory cells of the memory array during test, the programming voltage supply is prevented from being applied to a selected column line and all rows in the memory array are deselected simultaneously.

Input/output checker for a memory array

Architecture for a memory device and a method for employing the architecture for testing of the memory device are provided. In a memory device such as a one-time programmable EPROM, an extra row and an extra column of memory cells are added to the regular array. The extra column is configured so that, during a first test configuration, a sense device connected to the column line of the extra column of cells will detect whether exactly one row line of the correct parity is selected in response to input of a row address. Similarly, the extra row is configured so that the sense amp connected to the column lines of the regular array, can determine whether exactly one column line of the correct parity from the regular array is selected in response to input of a column address. The row decoder and row address lines are tested separately from the testing of the column decoder and column address lines. In this fashion, an EPROM can be tested to obtain single fault coverage for faults in address logic (including address inputs) and certain faults in a memory array without the need to write or program a memory cell. This permits practical testing for the above-mentioned coverage for EPROMs which cannot feasibly be erased such as one-time programmable (OTP) EPROMs.

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Sunnyvale, CA, United States of America

Varkey Paul Alapat