Intel Corporation

Varin Udompanyanan

Jeffrey E Smith

Stanley Steve Kulick

Suneeta Sah

Chitra Natarajan

Hrishikesh S Pai

Memory bandwidth may be enhanced by reordering read and write requests to memory. A read queue can hold multiple read requests and a write queue can hold multiple write requests. By examining the contents of the queues, the order in which the read and write requests are presented to memory may be changed to avoid or minimize page replace conflicts, DIMM turn around conflicts, and other types of conflicts that could otherwise impair the efficiency of memory operations.

Memory read/write reordering

An analog process/voltage/temperature (PVT) compensated buffer includes a differential amplifier providing a first output signal indicative of a difference between an input signal and a reference signal. The input signal is compatible with a first type of logic. An active gain stage is coupled to translate the first output signal to a second output signal. The second output signal is compatible with a second type of logic. The differential amplifier and the active gain stage are coupled to receive a process/voltage/temperature (PVT) compensation signal. In one embodiment, the first type of logic is Gunning Transceiver Logic (GTL) and the second type of logic is complementary metal oxide semiconductor (CMOS) logic.

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Hillsboro, OR, United States of America

Varin Udompanyanan